Archives

There are prudent reasons for not using too much of the FPGA’s resources, because one almost always has to insert more logic to fix a failing timing path or a functionality bug. Even back in college, the digital systems professor made it a rule that we could only use up to 70% of the logic resources for our senior […]

Continue Reading

It is common knowledge that Vivado uses an analytical place and route engine for better and more predictable design closure, and in the process, got rid of the “cost table” (also commonly known as random seeds) user options. What may be less well-known is that designers still have ways to introduce randomness into Vivado placement, and […]

Continue Reading

The notion of a self-driving or autonomous vehicle is firmly embedded in the collective consciousness; we’ve come quite a way since the days when such things were the stuff of science fiction. Now everyone knows what a self-driving car is, and quite possible has seen one in action on nearby roads. In search of timing closure… […]

Continue Reading

Of all the good things that OpenCL promises, the most attractive proposition is how different processors and cores in a multi-compute-core system can be utilised and maximised with a single programming framework. The ability to combine processing modules of different capabilities to perform particular tasks is, of course, the heterogenous computing concept that has been […]

Continue Reading