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The latest news from the Plunify team

The Auto Placement recipe in InTime now supports Quartus Prime Pro Edition (in addition to Quartus-II and Quartus Prime Std Edition). Recall from Automatic placement adjustments in Quartus that the Auto Placement recipe analyses the locations of failing timing paths, and re-locates them based on what the tool learns about the design’s characteristics, without changing any source […]

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While LogicLock assignments enable users to constrain their Quartus designs’ placement locations as part of floor-planning, at Plunify we’ve always been thinking about intelligently doing targeted LogicLock adjustments to improve design performance. This idea has now been implemented into a new recipe in InTime 1.6.0 called Auto Placement. The new Auto Placement recipe performs automatic placement adjustments to […]

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There are prudent reasons for not using too much of the FPGA’s resources, because one almost always has to insert more logic to fix a failing timing path or a functionality bug. Even back in college, the digital systems professor made it a rule that we could only use up to 70% of the logic resources for our senior […]

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It is common knowledge that Vivado uses an analytical place and route engine for better and more predictable design closure, and in the process, got rid of the “cost table” (also commonly known as random seeds) user options. What may be less well-known is that designers still have ways to introduce randomness into Vivado placement, and […]

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The notion of a self-driving or autonomous vehicle is firmly embedded in the collective consciousness; we’ve come quite a way since the days when such things were the stuff of science fiction. Now everyone knows what a self-driving car is, and quite possible has seen one in action on nearby roads. In search of timing closure… […]

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Of all the good things that OpenCL promises, the most attractive proposition is how different processors and cores in a multi-compute-core system can be utilised and maximised with a single programming framework. The ability to combine processing modules of different capabilities to perform particular tasks is, of course, the heterogenous computing concept that has been […]

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InTime version 1.5.11 is officially launched today. We haven’t been describing our last few releases as we have been fine-tuning them based on customers’ requirements. Today, we are proud to finally announce these improvements! “Deep Dive” recipe This recipe was born out of the differences in the results between InTime’s “Default” recipe and its “Placement Seed […]

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I think that most of us have experienced times when we were steadily going about our lives, absorbed in our daily routines and tasks, often content in the knowledge that whatever it was, we were making steady progress on all fronts; and then life suddenly throws a curveball. Imagine a person whom you regard as […]

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Oh! The paint hasn’t dried on my Vivado 2016.1 blogpost and 2016.2 is already out! The early months of 2016 saw the release of Vivado 2016.1. We naturally assumed that it would be better than the previous version, given what we heard from beta users and developers. In many cases, users usually base their opinions […]

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Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (“Quartus”) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project. Will Quartus always run Partition Merge? If not, why?Quartus tries […]

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