Blog

The latest news from the Plunify team

Oh! The paint hasn’t dried on my Vivado 2016.1 blogpost and 2016.2 is already out! The early months of 2016 saw the release of Vivado 2016.1. We naturally assumed that it would be better than the previous version, given what we heard from beta users and developers. In many cases, users usually base their opinions […]

Continue Reading

Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (“Quartus”) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project. Will Quartus always run Partition Merge? If not, why?Quartus tries […]

Continue Reading

In this edition we have some exciting updates about our new office in East Singapore, new Sales Reps onboard, an exciting investment announcement and last but not least, the upcoming release of InTime version 1.4.4. Plunify opens new headquarters in eastern Singapore Plunify appoints new reps in Beijing and Israel New InTime software version 1.4.4 […]

Continue Reading

An evaluation customer made an interesting comment recently. Due to the rigorous nature of InTime’s approach, we’d often get comments like, “You mean this takes 100 compilations more than usual?!” This time it was, “I need to evaluate InTime more as it met timing too quickly.” It felt like a compliment hidden within a complaint, […]

Continue Reading

Once in a while we come across cool stuff like this! Have fun! Check them out: Zero Characters Left: DIY FPGA-based HDMI ambient lighting “Ambient lighting is a technique that creates light effects around the television that correspond to the video content. It has been pioneered by Philips under the brand Ambilight. In this project we […]

Continue Reading

News of Tabula’s closure was naturally a big thing to people in the industry. For years, Tabula had been the shiny, young FPGA company with lots of talent and funding. Not that Tabula stayed a startup for long, given the considerable resources that it amassed. Many former colleagues had gone over to Tabula over the […]

Continue Reading

One of the questions that FPGA designers wonder and sometimes even argue about, is: Should the implementation tools focus on Worst Slack (WS) or Total Negative Slack (TNS)? FPGA tools typically devote more attention to WS, but there are tradeoffs. If WS is small yet many paths fail timing, then TNS can be huge. Similarly, […]

Continue Reading

http://eecatalog.com/chipdesign/2015/02/04/the-coming-year-in-eda-what-will-shape-2015/ Hamhua Ng, CEO of Plunify said: “There is much truth in the saying, ‘Those who don’t learn from history are doomed to repeat it,’ especially in the data-driven world that we live in today. It seems like every retailer, social network and financial institution is analyzing and finding patterns in the data that we […]

Continue Reading

EDA Past, Present, and Future with Lucio Lanza.Another amazing interview from one of our investors. http://www.eejournal.com/archives/articles/20141219-fishfry/

Continue Reading

Saw this interesting post about names people come up with for their companies. Ours is mentioned within although the origin of “Plunify” is probably not that interesting compared to some of the others! http://www10.edacafe.com/blogs/thebrekertrekker/2014/12/16/guest-post-whats-in-a-name/ For the record, we named our FPGA timing closure and optimization tool InTime because we wanted to help engineers get home […]

Continue Reading