What is AI Lab? Plunify’s AI Lab is a cloud-based development environment that can be pre-loaded and pre-configured with Machine Learning / Artificial Intelligence (AI) software like CUDA and Caffe. AI Lab also supports FPGA tools like Vivado and SDSoc. Because of the ubiquity nature of cloud computing, AI Lab’s functions are available for every machine […]
As we get new requests for AI Lab and FPGA Expansion Pack in more geographical regions like China, we are receiving feedback (and complaints) about latency and responsiveness. In anticipation of an upcoming event involving AI Lab, we ran a series of simple networking tests to determine the latency, bandwidth and in general, real-life responsiveness […]
You may think that it’s impossible to run Vivado on a lightweight machine like a Chromebook. After all, FPGA design is a compute-heavy task that is only practical with your company’s workstations and high-performance servers. So how do we do it? Mission Impossible? Okay, we confess; We can’t bend the laws of physics so we […]
In FPGA design optimization, it is practically impossible to predict the effect of every possible placement and route in advance. Exploring the endless combinations of settings to find good ones is like navigating correctly through a teeming traffic thoroughfare. So drawing inspiration from autonomous driving that successfully solved the road navigation problems, how do you […]
Plunify’s newest FPGA Expansion Pack for Vivado is the latest addition to a suite of cloud-enabled tools on Plunify Cloud. This tool was created for FPGA designers who have explored and are ready or perhaps have already adopted the cloud. They can relate easily to the following account of a typical customer’s experience. Plunify has been […]
Today we announce an exciting new partnership with Xilinx to provide on-demand licenses of the best-in-class Vivado Design Suite HLx Editions software on the Plunify Cloud. Plunify Cloud is built upon the largest cloud provider – Amazon Web Services. What you can look forward to under the new Plunify-Xilinx agreement is a cloud-based platform encompassing […]
It is the start of a brand new day. You come to the office, open up a medical imaging design that met timing the day before and finds that a bugfix made by someone else has led to timing failures. In the demanding world of high-performance FPGA design, there is no free lunch. We take pains […]
Atomos is a manufacturer of high-quality video related recording devices. With offices all across the globe, Atomos has a clear vision — to revolutionize digital video production by combining smart workflows with simple operation to deliver cost-effective recording and conversion solutions for today’s video and film professionals. Challenges Atomos had four product designs to deliver […]
Introduction The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools […]
This whitepaper compares the effectiveness of two timing optimization methods: The InTime Default recipe provided by the InTime FPGA design optimization tool and another one commonly known as a “Seed Sweep”. InTime Default is a machine learning approach that finds good synthesis and place-and-route setting combinations for a design. It shares data insights across different […]