1.0Plunify Blog & Supporthttps://support.plunify.com/enKirvy Teohttps://support.plunify.com/en/author/kirvy/rich600338<blockquote class="wp-embedded-content"><a href="https://support.plunify.com/en/2012/01/20/biggest-challenges-in-fpga-design/">Biggest Challenges in FPGA Design</a></blockquote> <script type='text/javascript'> <!--//--><![CDATA[//><!-- /*! This file is auto-generated */ !function(d,l){"use strict";var e=!1,n=!1;if(l.querySelector)if(d.addEventListener)e=!0;if(d.wp=d.wp||{},!d.wp.receiveEmbedMessage)if(d.wp.receiveEmbedMessage=function(e){var t=e.data;if(t)if(t.secret||t.message||t.value)if(!/[^a-zA-Z0-9]/.test(t.secret)){for(var r,i,a,s=l.querySelectorAll('iframe[data-secret="'+t.secret+'"]'),n=l.querySelectorAll('blockquote[data-secret="'+t.secret+'"]'),o=new RegExp("^https?:$","i"),c=0;c<n.length;c++)n[c].style.display="none";for(c=0;c<s.length;c++)if(r=s[c],e.source===r.contentWindow){if(r.removeAttribute("style"),"height"===t.message){if(1e3<(a=parseInt(t.value,10)))a=1e3;else if(~~a<200)a=200;r.height=a}if("link"===t.message)if(i=l.createElement("a"),a=l.createElement("a"),i.href=r.getAttribute("src"),a.href=t.value,o.test(a.protocol))if(a.host===i.host)if(l.activeElement===r)d.top.location.href=t.value}}},e)d.addEventListener("message",d.wp.receiveEmbedMessage,!1),l.addEventListener("DOMContentLoaded",t,!1),d.addEventListener("load",t,!1);function t(){if(!n){n=!0;for(var e,t,r=-1!==navigator.appVersion.indexOf("MSIE 10"),i=!!navigator.userAgent.match(/Trident.*rv:11\./),a=l.querySelectorAll("iframe.wp-embedded-content"),s=0;s<a.length;s++){if(!(e=a[s]).getAttribute("data-secret"))t=Math.random().toString(36).substr(2,10),e.src+="#?secret="+t,e.setAttribute("data-secret",t);if(r||i)(t=e.cloneNode(!0)).removeAttribute("security"),e.parentNode.replaceChild(t,e)}}}}(window,document); //--><!]]> </script><iframe sandbox="allow-scripts" security="restricted" src="https://support.plunify.com/en/2012/01/20/biggest-challenges-in-fpga-design/embed/" width="600" height="338" title="“Biggest Challenges in FPGA Design” — Plunify Blog & Support" frameborder="0" marginwidth="0" marginheight="0" scrolling="no" class="wp-embedded-content"></iframe>A poll on the challenges associated with FPGA design in an FPGA discussion group on LinkedIn caught my attention recently. Conducted by Cuong Nguyen from EDA Direct, it drew several lengthy comments. Poll: FPGA Design Challenges My vote went to Timing Closure - definitely one of the most frustrating and time-consuming classes of problems for […]https://3.bp.blogspot.com/-kp9bnXL7gw0/T0IPxFOfOwI/AAAAAAAAAMA/Js1aIgwwECw/s320/Screen+Shot+2012-02-20+at+5.11.21+PM.png