{"id":1570,"date":"2016-06-06T02:03:00","date_gmt":"2016-06-06T02:03:00","guid":{"rendered":""},"modified":"2018-06-12T02:00:38","modified_gmt":"2018-06-12T02:00:38","slug":"a-sum-of-partitions","status":"publish","type":"post","link":"https:\/\/support.plunify.com\/en\/2016\/06\/06\/a-sum-of-partitions\/","title":{"rendered":"A Sum of Part(ition)s"},"content":{"rendered":"<p>Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (\"Quartus\") design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project.<\/p>\n<p><span style=\"font-family: inherit\"><b>Will Quartus always run Partition Merge? If not, why?<\/b><\/span><br \/>\nQuartus tries to detect partitions in your design and only runs Partition Merge if there is at least one partition.<\/p>\n<p>For example, if you import a Quartus Exported Partition File (.qxp file) into your project and designate it as a partition, Quartus will run Partition Merge during the compilation process.<br \/>\nHowever, if you simply import the same .qxp netlist as a source file but neglect to designate it as a partition, Quartus will NOT run Partition Merge automatically.<\/p>\n<p><b>Okay, so what?<\/b><br \/>\nWorking with a customer, we found that timing results improved significantly (see Table 1 below) when Partition Merge was run versus when it was not run.<\/p>\n<table style=\"background-color: #99ffff;width: 100%px;border: 0px\" cellspacing=\"3\" cellpadding=\"3\">\n<tbody>\n<tr>\n<th style=\"text-align: center\"><span style=\"font-weight: normal;text-align: justify\">Arria 10 design<\/span><\/th>\n<th style=\"text-align: center\"><span style=\"text-align: justify\">Without Partition Merge<\/span><br \/>\n<span style=\"font-weight: normal;text-align: justify\">(.qxp as source file)<\/span><\/th>\n<th style=\"text-align: center\">With Partition Merge<br \/>\n<span style=\"font-weight: normal\">(same .qxp as a partition)<\/span><\/th>\n<\/tr>\n<tr>\n<td>\n<div style=\"text-align: center\"><b>Total Negative Slack (TNS)<\/b><\/div>\n<\/td>\n<td>\n<div style=\"text-align: center\">-1533.727 ns<\/div>\n<\/td>\n<td>\n<div style=\"text-align: center\">-387.006 ns<\/div>\n<\/td>\n<\/tr>\n<tr>\n<td>\n<div style=\"text-align: center\"><b>Worst Slack (Setup \/ Hold)<\/b><\/div>\n<\/td>\n<td>\n<div style=\"text-align: center\">-0.807 ns<\/div>\n<\/td>\n<td>\n<div style=\"text-align: center\">-0.516 ns<\/div>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p style=\"text-align: center\">Table 1: Timing results with and without Partition Merge<\/p>\n<p>Intuitively, the above results seem logical because Partition Merge performs optimizations such as resource sharing, thus affecting timing performance. The <i>\"gotcha\"<\/i> here is that one might think that importing a netlist automatically triggers Partition Merge, but no -- you would have to explicitly declare it as a partition before things work as expected.<\/p>\n<p>How we found this 'bug' was actually rather interesting -- InTime exported a result for a customer and the customer proceeded to reproduce the same result in Quartus, but obtained a much worse result (exactly what you see in Table 1 above). After banging our heads against the wall for a couple of days, we finally found the cause of the differences and documented it here in case someone else runs into a similar predicament.<\/p>\n<div style=\"margin-bottom: 0in\">At the end of the day, what matters is that you should be getting the best timing performance that your FPGA tool can produce, with minimal fuss.<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (&#8220;Quartus&#8221;) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project. Will Quartus always run Partition Merge? If not, why? Quartus [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spay_email":"","jetpack_publicize_message":"","jetpack_is_tweetstorm":false,"_links_to":"","_links_to_target":""},"categories":[206],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v17.0 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>A Sum of Part(ition)s - Plunify Blog &amp; Support<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/support.plunify.com\/en\/2016\/06\/06\/a-sum-of-partitions\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"A Sum of Part(ition)s - Plunify Blog &amp; Support\" \/>\n<meta property=\"og:description\" content=\"Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (&quot;Quartus&quot;) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. 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