{"id":1985,"date":"2017-04-19T02:04:46","date_gmt":"2017-04-19T02:04:46","guid":{"rendered":"http:\/\/support.plunify.com\/en\/?p=1985"},"modified":"2018-05-23T07:20:39","modified_gmt":"2018-05-23T07:20:39","slug":"whitepaper-timing-closure-is-vital-to-fpga-design","status":"publish","type":"post","link":"https:\/\/support.plunify.com\/en\/2017\/04\/19\/whitepaper-timing-closure-is-vital-to-fpga-design\/","title":{"rendered":"Whitepaper: Timing Closure is vital to FPGA design"},"content":{"rendered":"<p>If you are reading this, the odds are that you or someone in your company is facing\/has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application.<\/p>\n<p>Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified people to speak about this topic. <a href=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/08\/WhitePaper-Timing-closure-in-FPGAs-is-critical.pdf\" target=\"_blank\">Click\u00a0here <\/a>to view his perspectives on.<\/p>\n<h4><strong>Topics covered in this whitepaper<\/strong><\/h4>\n<ul>\n<li>Planning for timing closure.<\/li>\n<li>The vendor tools do a remarkably good job at design compilation for the general case but sometimes they can fall short.<\/li>\n<li>Why is timing closure so difficult for the vendor FPGA compilation tools?<\/li>\n<li>What to do if you cannot achieve timing closure?<\/li>\n<li>How does the <a href=\"https:\/\/www.plunify.com\/en\/intime\/\">InTime timing closure tool<\/a> help?<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>If you are reading this, the odds are that you or someone in your company is facing\/has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application. Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified people to [&hellip;]<\/p>\n","protected":false},"author":10,"featured_media":2261,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spay_email":"","jetpack_publicize_message":"","jetpack_is_tweetstorm":false,"_links_to":"","_links_to_target":""},"categories":[205,206],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v17.0 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Whitepaper: Timing Closure is vital to FPGA design<\/title>\n<meta name=\"description\" content=\"Timing closure is the single most important obstacle to implementing a successful FPGA application. A careful plan is the key to reach the timing target.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/support.plunify.com\/en\/2017\/04\/19\/whitepaper-timing-closure-is-vital-to-fpga-design\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Whitepaper: Timing Closure is vital to FPGA design\" \/>\n<meta property=\"og:description\" content=\"Timing closure is the single most important obstacle to implementing a successful FPGA application. A careful plan is the key to reach the timing target.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/support.plunify.com\/en\/2017\/04\/19\/whitepaper-timing-closure-is-vital-to-fpga-design\/\" \/>\n<meta property=\"og:site_name\" content=\"Plunify Blog &amp; Support\" \/>\n<meta property=\"article:published_time\" content=\"2017-04-19T02:04:46+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2018-05-23T07:20:39+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/i1.wp.com\/support.plunify.com\/en\/wp-content\/uploads\/sites\/5\/2017\/03\/blog_header-e1492571147462.jpg?fit=600%2C402&#038;ssl=1\" \/>\n\t<meta property=\"og:image:width\" content=\"600\" \/>\n\t<meta property=\"og:image:height\" content=\"402\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"harnhua\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Organization\",\"@id\":\"https:\/\/support.plunify.com\/en\/#organization\",\"name\":\"Plunify-Support\",\"url\":\"https:\/\/support.plunify.com\/en\/\",\"sameAs\":[],\"logo\":{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/support.plunify.com\/en\/#logo\",\"inLanguage\":\"en-US\",\"url\":\"https:\/\/i1.wp.com\/support.plunify.com\/en\/wp-content\/uploads\/sites\/5\/2016\/05\/Plunify_Logo_Outline_TranspBG_sm.png?fit=600%2C159&ssl=1\",\"contentUrl\":\"https:\/\/i1.wp.com\/support.plunify.com\/en\/wp-content\/uploads\/sites\/5\/2016\/05\/Plunify_Logo_Outline_TranspBG_sm.png?fit=600%2C159&ssl=1\",\"width\":600,\"height\":159,\"caption\":\"Plunify-Support\"},\"image\":{\"@id\":\"https:\/\/support.plunify.com\/en\/#logo\"}},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/support.plunify.com\/en\/#website\",\"url\":\"https:\/\/support.plunify.com\/en\/\",\"name\":\"Plunify Blog &amp; Support\",\"description\":\"Everything you need to know about Plunify products\",\"publisher\":{\"@id\":\"https:\/\/support.plunify.com\/en\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/support.plunify.com\/en\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/support.plunify.com\/en\/2017\/04\/19\/whitepaper-timing-closure-is-vital-to-fpga-design\/#primaryimage\",\"inLanguage\":\"en-US\",\"url\":\"https:\/\/i1.wp.com\/support.plunify.com\/en\/wp-content\/uploads\/sites\/5\/2017\/03\/blog_header-e1492571147462.jpg?fit=600%2C402&ssl=1\",\"contentUrl\":\"https:\/\/i1.wp.com\/support.plunify.com\/en\/wp-content\/uploads\/sites\/5\/2017\/03\/blog_header-e1492571147462.jpg?fit=600%2C402&ssl=1\",\"width\":600,\"height\":402},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/support.plunify.com\/en\/2017\/04\/19\/whitepaper-timing-closure-is-vital-to-fpga-design\/#webpage\",\"url\":\"https:\/\/support.plunify.com\/en\/2017\/04\/19\/whitepaper-timing-closure-is-vital-to-fpga-design\/\",\"name\":\"Whitepaper: Timing Closure is vital to FPGA design\",\"isPartOf\":{\"@id\":\"https:\/\/support.plunify.com\/en\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/support.plunify.com\/en\/2017\/04\/19\/whitepaper-timing-closure-is-vital-to-fpga-design\/#primaryimage\"},\"datePublished\":\"2017-04-19T02:04:46+00:00\",\"dateModified\":\"2018-05-23T07:20:39+00:00\",\"description\":\"Timing closure is the single most important obstacle to implementing a successful FPGA application. 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