{"id":2428,"date":"2017-05-31T07:38:03","date_gmt":"2017-05-31T07:38:03","guid":{"rendered":"http:\/\/support.plunify.com\/en\/?p=2428"},"modified":"2019-04-25T05:55:10","modified_gmt":"2019-04-25T05:55:10","slug":"xilinx-fpga-comparison","status":"publish","type":"post","link":"https:\/\/support.plunify.com\/en\/2017\/05\/31\/xilinx-fpga-comparison\/","title":{"rendered":"Xilinx FPGA Toolchain Comparison: Vivado 2016.4 VS Vivado 2017.1"},"content":{"rendered":"

Xilinx FPGA Performance Evaluation for\u00a0Vivado 2016.4 and Vivado 2017.1 using InTime<\/a>.<\/h2>\n

Overall, we conducted three experiments pitting Vivado 2016.4 against Vivado 2017.1. Under our test conditions, Vivado 2017.1 achieves slightly better results in Experiment 1, while total Negative Slack and Worst Slack in Vivado 2017.1 were much better in Experiments 2 and 3. <\/span><\/p>\n

Methods<\/h2>\n

For this performance test, we use a modified version of the Vivado example \u201ccpu\u201d design with the target device: xc7k70tfbg676-2. The design\u2019s constraints were modified to make it fail timing.<\/span><\/p>\n

Compare the two toolchains via the following steps:<\/span><\/p>\n

    \n
  1. InTime generates compilation settings for Vivado 2016.4. Compile using the same settings on Vivado 2017.1.<\/span><\/li>\n
  2. InTime generates compilation settings for Vivado 2017.1. Compile using the same settings on Vivado 2016.4.<\/span><\/li>\n<\/ol>\n

    Comparison between the 2 toolchains will be done using the following experiments:<\/span><\/p>\n