{"id":1570,"date":"2016-06-06T02:03:00","date_gmt":"2016-06-06T02:03:00","guid":{"rendered":"http:\/\/support.plunify.com\/jp\/2016\/06\/06\/a-sum-of-partitions\/"},"modified":"2016-06-06T02:03:00","modified_gmt":"2016-06-06T02:03:00","slug":"a-sum-of-partitions","status":"publish","type":"post","link":"https:\/\/support.plunify.com\/jp\/2016\/06\/06\/a-sum-of-partitions\/","title":{"rendered":"A Sum of Part(ition)s"},"content":{"rendered":"

Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (\"Quartus\") design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project.<\/p>\n

<\/a><\/a>Will Quartus always run Partition Merge? If not, why?<\/b><\/span>
Quartus tries to detect partitions in your design and only runs Partition Merge if there is at least one partition.<\/p>\n

For example, if you import a Quartus Exported Partition File (.qxp file) into your project and designate it as a partition, Quartus will run Partition Merge during the compilation process.
However, if you simply import the same .qxp netlist as a source file but neglect to designate it as a partition, Quartus will NOT run Partition Merge automatically.<\/p>\n

Okay, so what?<\/b>
Working with a customer, we found that timing results improved significantly (see Table 1 below) when Partition Merge was run versus when it was not run.<\/p>\n

\n

<\/span><\/div>\n
\n\n\n\n\n\n
Arria 10 design<\/span><\/th>\nWithout Partition Merge<\/span>
(.qxp as source file)<\/span><\/th>\n		With Partition Merge
(same .qxp as a partition)<\/span><\/th>\n<\/tr>\n
\n
Total Negative Slack (TNS)<\/b><\/div>\n<\/td>\n
\n
-1533.727 ns<\/div>\n<\/td>\n
\n
-387.006 ns<\/div>\n<\/td>\n<\/tr>\n
\n
Worst Slack (Setup \/ Hold)<\/b><\/div>\n<\/td>\n
\n
-0.807 ns<\/div>\n<\/td>\n
\n
-0.516 ns<\/div>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
Table 1: Timing results with and without Partition Merge<\/div>\n

Intuitively, the above results seem logical because Partition Merge performs optimizations such as resource sharing, thus affecting timing performance. The \"gotcha\"<\/i> here is that one might think that importing a netlist automatically triggers Partition Merge, but no -- you would have to explicitly declare it as a partition before things work as expected.<\/p>\n

How we found this 'bug' was actually rather interesting -- InTime exported a result for a customer and the customer proceeded to reproduce the same result in Quartus, but obtained a much worse result (exactly what you see in Table 1 above). After banging our heads against the wall for a couple of days, we finally found the cause of the differences and am documenting it here in case someone else runs into a similar predicament.<\/p><\/div>\n

At the end of the day, what matters is that you should be getting the best timing performance that your FPGA tool can produce, with minimal fuss.<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (“Quartus”) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project. Will Quartus always run Partition Merge? If not, why?Quartus tries […]<\/p>\n","protected":false},"author":5,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_links_to":"","_links_to_target":""},"categories":[98],"tags":[],"yoast_head":"\nA Sum of Part(ition)s - Plunify \u65e5\u672c\u8a9e\u30d8\u30eb\u30d7\u30c7\u30b9\u30af<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/support.plunify.com\/jp\/2016\/06\/06\/a-sum-of-partitions\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"A Sum of Part(ition)s - Plunify \u65e5\u672c\u8a9e\u30d8\u30eb\u30d7\u30c7\u30b9\u30af\" \/>\n<meta property=\"og:description\" content=\"Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II ("Quartus") design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. 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