Recently, one of us posted a question on a discussion forum about how important synthesis, place-and-route time to developers?<\/p>\n
There were quite a few responses; most people agreed that as FPGAs and FPGA designs get more and more complex, implementation time becomes a larger portion of the development budget or project timeline.<\/p>\n
As silicon process technology gets smaller, increasing the number of gates the software tools have to route for FPGAs, makers also add more complex blocks in the FPGAs. As FPGAs become more complex, the time spent to design, implement and debug increases. One needs more iterations to complete a design--hence how fast the tools crunch one's design directly affects when the design will be completed.<\/p>\n
Some respondents said that there are just too many other variables that are equally important.
Which we take to mean, there are many areas for improvement in the FPGA world!<\/p>\n
Others proposed a higher-level view: that we should take a step back and focus on improving design methodology instead.
That's where more gains could potentially be made.<\/p>\n