{"id":2037,"date":"2016-10-31T07:39:22","date_gmt":"2016-10-31T07:39:22","guid":{"rendered":"http:\/\/support.plunify.com\/en\/?p=1794"},"modified":"2016-10-31T07:39:22","modified_gmt":"2016-10-31T07:39:22","slug":"opencl-living-heterogeneously","status":"publish","type":"post","link":"https:\/\/support.plunify.com\/jp\/2016\/10\/31\/opencl-living-heterogeneously\/","title":{"rendered":"OpenCL: Living heterogeneously"},"content":{"rendered":"

Of all the good things that OpenCL promises, the most attractive proposition is how different processors and cores in a multi-compute-core system can be utilised and maximised with a single programming framework. The ability to combine processing modules of different capabilities to perform particular tasks is, of course, the heterogenous computing concept that has been talked about over the years.<\/p>\n

\"screen-shot-2016-10-29-at-12-38-13-am\"Host: \"Doesn't matter what device runs my C code,
\nas long as the most effective one does.\"<\/p>\n

Being in FPGA land most of the time, naturally we at dream about how software programmers can easily port relevant functions in C, C++, etc. to FPGAs, smoothly getting 10x and more performance gains. As usage of FPGAs keep expanding into new areas, we also want C-to-RTL tools to work really well so that good FPGA designs can propagate and show their value as efficient and fast processing engines. However, because of the formidable difficulties in producing good FPGA-ready RTL for every possible software function, there have been many false dawns over the years in terms of \"Is this finally the go-to C-to-RTL tool?\"<\/p>\n

Certainly there have been glowing assessments on the business-readiness of OpenCL for FPGA flows<\/a>\u00a0- in this particular instance, for financial computation. But without going into\u00a0what the best OpenCL for FPGA or High-Level Synthesis (HLS) tool is, let's\u00a0take a look\u00a0at one of the common\u00a0issues facing a software developer when attempting a C-to-RTL flow; an issue that can be said to\u00a0impair the ease-of-use and adoption of OpenCL tools. Both software and hardware (in the traditional meaning of these words) knowledge are required in this type of porting effort.<\/p>\n

Loop unrolling<\/strong><\/p>\n

In EE and CS classes, we've been exposed to loop unrolling, a technique that\u00a0generally trades hardware resources for faster execution times. Loop unrolling requires an understanding of data dependencies and it seems, the underlying hardware resources. The latter is where confusion and some amount of hair-pulling can occur.<\/p>\n

Take for instance, this (dated but still relevant) post:
\nhttps:\/\/forums.xilinx.com\/t5\/High-Level-Synthesis-HLS\/Why-I-can-only-Unroll-2-times\/m-p\/461728\/highlight\/true#M1789<\/a><\/p>\n

Scenario:<\/strong><\/p>\n

Vivado HLS was used to convert a software function into RTL:<\/p>\n

void matpro(const float v[15],float d[15]){
\n<\/span>char i,i111,i112;
\n<\/span>float b_StateVectors[15];
\n<\/span>\u00a0 for (i = 0; i < 15; i++) {
\n<\/span>\u00a0 \u00a0 d[i]=v[i]*b_StateVectors[i];
\n<\/span>\u00a0 \u00a0}
\n<\/span>}<\/span><\/p>\n

There are no dependencies in the computation, and the OP felt that\u00a0the tool should be able to use FPGA resources to unroll the loop and reduce the number of loop iterations from 15 to N. N can be 1 if there are enough resources to do the calculation. However, the tool's resulting analysis showed that the loop was only unrolled by 2x, plus some pipelining.<\/p>\n

Why only 2x?<\/p>\n

With advice from another user, the OP found that setting a ARRAY_PARTITION directive to use registers instead of 2-port memories was the answer. Because if you use a 2-port memory in this case, the amount of data transfer operations that can happen is severely limited.<\/p>\n

Implications<\/strong><\/p>\n

One\u00a0takeaway is that user input is required as part of the C-to-RTL conversion in order to achieve an optimal design. The tools are continuously improving, so over time, parameters such as those mentioned above will be automatically included as the software becomes better at it. On the user's side of things, deeper knowledge of the FPGA devices and design tools will help bridge the gap, assuming the software engineer is interested in those details.<\/p>\n

More to come as we explore this area of optimisation to make InTime<\/a> tweak C-to-RTL flows.<\/p>\n

References<\/strong><\/p>\n