An evaluation customer made an interesting comment recently. Due to the rigorous nature of InTime’s approach, we’d often get comments like, “You mean this takes 100 compilations more than usual?!” This time it was, “I need to evaluate InTime more as it met timing too quickly.” It felt like a compliment hidden within a complaint, […]
Once in a while we come across cool stuff like this! Have fun! Check them out: Zero Characters Left: DIY FPGA-based HDMI ambient lighting “Ambient lighting is a technique that creates light effects around the television that correspond to the video content. It has been pioneered by Philips under the brand Ambilight. In this project we […]
News of Tabula’s closure was naturally a big thing to people in the industry. For years, Tabula had been the shiny, young FPGA company with lots of talent and funding. Not that Tabula stayed a startup for long, given the considerable resources that it amassed. Many former colleagues had gone over to Tabula over the […]
One of the questions that FPGA designers wonder and sometimes even argue about, is: Should the implementation tools focus on Worst Slack (WS) or Total Negative Slack (TNS)? FPGA tools typically devote more attention to WS, but there are tradeoffs. If WS is small yet many paths fail timing, then TNS can be huge. Similarly, […]
http://eecatalog.com/chipdesign/2015/02/04/the-coming-year-in-eda-what-will-shape-2015/ Hamhua Ng, CEO of Plunify said: “There is much truth in the saying, ‘Those who don’t learn from history are doomed to repeat it,’ especially in the data-driven world that we live in today. It seems like every retailer, social network and financial institution is analyzing and finding patterns in the data that we […]
EDA Past, Present, and Future with Lucio Lanza.Another amazing interview from one of our investors. http://www.eejournal.com/archives/articles/20141219-fishfry/
Saw this interesting post about names people come up with for their companies. Ours is mentioned within although the origin of “Plunify” is probably not that interesting compared to some of the others! http://www10.edacafe.com/blogs/thebrekertrekker/2014/12/16/guest-post-whats-in-a-name/ For the record, we named our FPGA timing closure and optimization tool InTime because we wanted to help engineers get home […]
Last month we released InTime v1.2, and we’ve been pushing out a number of incremental updates ever since. While the past few versions have been all about introducing new kick-ass features into InTime, this time we focused on working out the kinks. Here are the highlights of this version. New “Seeded Effort Level Exploration” Recipe Like […]