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The latest news from the Plunify team

The difference between passing and failing timing can be tiny, but failing by 500ps is just as frustrating as falling short by 5ns. Clock Margin Exploration is a new recipe in InTime version 2.3.0 that over-constrains the user’s design, potentially yielding better timing results without modifying the design. The idea is to apply “Clock Margin” adjustments […]

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Design Automation Conference 2017 in Austin, TX came and went before one could say, “Congress Bridge Bats!” A big Thank You to everyone who came by. It was very good getting to know you and hear about your design challenges and requirements — FPGA as well as ASIC ones. Devices and designs are both getting […]

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In this blog post we evaluate the performance of Vivado 2016.4 and Vivado 2017.1 using InTime. Overall, we conducted three experiments pitting 2016.4 against 2017.1. Under our test conditions, Vivado 2017.1 achieves better results, albeit the difference was slight for Experiment 1. Total Negative Slack and Worst Slack in Vivado 2017.1 were much better in Experiments […]

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Ever wondered how efficient InTime when it is helping you and your team optimize FPGA designs? When using the InTime Private Cloud, are you curious about whether your team has sufficient licenses to meet performance targets on time? Is there a need to increase the number of licenses? These questions represent important metrics for decision maker(s) […]

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Introduction One of our most common customer requests is for a smaller number of compilation runs to get to timing closure. For example, can InTime meet timing in 50 runs instead of 100 on average? Well, that depends; InTime generally has an idea of what settings will help your design meet timing, and in rare cases […]

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For those who know our history, Plunify was born in the cloud. Our very first prototype of InTime was developed, executed and tested on Amazon Web Services. During those days, we only had to contend with EC2, EBS and S3. We even had to implement AES encryption in S3 ourselves (nowadays it is a checkbox!). […]

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If you are reading this, the odds are that you or someone in your company is facing / has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application. Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified […]

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We are excited to announce the release of a new feature – Central Database (CD), in InTime. In previous versions of InTime, the visibility of compilation and analysis results is limited to individual users.  With CD, it gathers design data more efficiently across multiple users and different projects within your organization and enables sharing across different workstations and users. Below is […]

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Hi! We are happy to announce that InTime now supports the inheritance of Auto Placement assignments. This means that LogicLock or LogicLock Plus assignments created via the Auto Placement recipe will be passed onto its child revisions. For example, Tommy ran his design in InTime for three rounds. 1st round  : InTime Default 2nd round: Auto Placement 3rd […]

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Based on feedback, we understand that it is sometimes not easy for users to send us InTime log files when they encounter an issue. This is because the log files may contain what is seen as confidential information. In order to set our customers at ease, we have included a Tcl script to replace sensitive […]

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