InTime

So, I have an Arria 10 design, should I upgrade to Quartus 17.0? To answer this question, we used InTime tool to run through 60 different synthesis and place-and-route parameter configurations were generated by our Default recipe. Method We used an Arria 10 design (Device: 10AX115U3F45E2SGE3) for the experiment. The test was conducted as follows: InTime generates […]

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Optimizing design performance with InTime and Xilinx tools Executive Summary This whitepaper describes how InTime works with Xilinx software to optimize FPGA timing performance by adjusting compilation parameters and running builds in parallel. InTime uses machine learning to determine the best combination of synthesis and place-&-route settings for an FPGA design. Combined with compute servers, […]

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Besides fixing a few bugs, for example, in the Clock Margin recipe introduced in version 2.3,  the new features for InTime 2.4 mainly focus on providing more convenience and enhancing usability. Here is a quick summary. Auto detect FPGA tool chain and license information One of the biggest issues faced by users in large organizations […]

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The difference between passing and failing timing can be tiny, but failing by 500ps is just as frustrating as falling short by 5ns. Clock Margin Exploration is a new recipe in InTime version 2.3.0 that over-constrains the user’s design, potentially yielding better timing results without modifying the design. The idea is to apply “Clock Margin” adjustments […]

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Ever wondered how efficient InTime when it is helping you and your team optimize FPGA designs? When using the InTime Private Cloud, are you curious about whether your team has sufficient licenses to meet performance targets on time? Is there a need to increase the number of licenses? These questions represent important metrics for decision maker(s) […]

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Introduction One of our most common customer requests is for a smaller number of compilation runs to get to timing closure. For example, can InTime meet timing in 50 runs instead of 100 on average? Well, that depends; InTime generally has an idea of what settings will help your design meet timing, and in rare cases […]

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If you are reading this, the odds are that you or someone in your company is facing / has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application. Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified […]

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We are excited to announce the release of a new feature – Central Database (CD), in InTime. In previous versions of InTime, the visibility of compilation and analysis results is limited to individual users.  With CD, it gathers design data more efficiently across multiple users and different projects within your organization and enables sharing across different workstations and users. Below is […]

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Hi! We are happy to announce that InTime now supports the inheritance of Auto Placement assignments. This means that LogicLock or LogicLock Plus assignments created via the Auto Placement recipe will be passed onto its child revisions. For example, Tommy ran his design in InTime for three rounds. 1st round  : InTime Default 2nd round: Auto Placement 3rd […]

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Based on feedback, we understand that it is sometimes not easy for users to send us InTime log files when they encounter an issue. This is because the log files may contain what is seen as confidential information. In order to set our customers at ease, we have included a Tcl script to replace sensitive […]

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