InTime

Recently we had an opportunity to optimize an FFT design generated from the Intel DSP Builder tool (in conjunction with MatLab and Simulink). This is an interesting project because the designer did not develop the RTL but generated the RTL from DSP Builder. Therefore a lot of the performance depends on how good the generated […]

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While we wait for the release of 2019 version of Vivado, we realize that we have missed our annual Vivado comparison post.  So here is the Vivado 2017.4 versus 2018.3 edition. For previous year’s results, please click here. The methods are the same as before. We use a modified version of the Vivado example “CPU” […]

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Many of us use 3rd-party IP to accelerate our development process and time-to-market. While IP reuse is certainly helpful, we see customers who are encountering timing and performance issues because of integration challenges. This problem becomes more apparent with design involving high-speed interfaces. Why High-speed Interfaces? Many of these problems have to do with designs […]

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Generated RTL code from a C-to-RTL tool is not easy to understand. Here is how to increase design performance without changing any RTL. Story High-level design enables a design to be captured in a concise and succinct manner, resulting in fewer errors and easier debugging. However, the oft-repeated concern is performance trade-off. Achieving high performance […]

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Cloud is shaping EDA like never before. Today, we are releasing the full InTime tool on the Plunify AI Lab platform. Announcing InTime on AI Lab InTime is officially included on AI Lab as one of the tools on the Plunify Cloud eco-system. This combines the cloud’s massive compute power to the ubiquitous of AI Lab platform to benefit more […]

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At the beginning of 2017, we published an article about running “seeds” in Vivado – Who Says You Can’t Use Random Seeds In Vivado?  Although Vivado does not support the “placement cost table” feature, InTime has a feature called “Placement Exploration”, which enables similar behavior without any impact on functionality. In this post, we are going […]

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In a previous post, we introduced a way to predict and abandon builds at the post-placement stage, skipping time- and resource-consuming routing stages that were not likely to yield good timing results. InTime users welcomed this approach, especially those who were designing with large FPGAs. We are thrilled to add this capability for our Quartus […]

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In FPGA design optimization, it is practically impossible to predict the effect of every possible placement and route in advance. Exploring the endless combinations of settings to find good ones is like navigating correctly through a teeming traffic thoroughfare. So drawing inspiration from autonomous driving that successfully solved the road navigation problems, how do you […]

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It is the start of a brand new day. You come to the office, open up a medical imaging design that met timing the day before and finds that a bugfix made by someone else has led to timing failures. In the demanding world of high-performance FPGA design, there is no free lunch. We take pains […]

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Atomos is a manufacturer of high-quality video related recording devices. With offices all across the globe, Atomos has a clear vision — to revolutionize digital video production by combining smart workflows with simple operation to deliver cost-effective recording and conversion solutions for today’s video and film professionals. Challenges Atomos had four product designs to deliver […]

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