InTime

At the beginning of 2017, we published an article about running “seeds” in Vivado – Who Says You Can’t Use Random Seeds In Vivado?  Although Vivado does not support the “placement cost table” feature, InTime has a feature called “Placement Exploration”, which enables similar behavior without any impact on functionality. In this post, we are going […]

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In a previous post, we introduced a way to predict and abandon builds at the post-placement stage, skipping time- and resource-consuming routing stages that were not likely to yield good timing results. InTime users welcomed this approach, especially those who were designing with large FPGAs. We are thrilled to add this capability for our Quartus […]

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In FPGA design optimization, it is practically impossible to predict the effect of every possible placement and route in advance. Exploring the endless combinations of settings to find good ones is like navigating correctly through a teeming traffic thoroughfare. So drawing inspiration from autonomous driving that successfully solved the road navigation problems, how do you […]

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It is the start of a brand new day. You come to the office, open up a medical imaging design that met timing the day before and finds that a bugfix made by someone else has led to timing failures. In the demanding world of high-performance FPGA design, there is no free lunch. We take pains […]

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Atomos is a manufacturer of high-quality video related recording devices. With offices all across the globe, Atomos has a clear vision — to revolutionize digital video production by combining smart workflows with simple operation to deliver cost-effective recording and conversion solutions for today’s video and film professionals. Challenges Atomos had four product designs to deliver […]

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Introduction The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools […]

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This whitepaper compares the effectiveness of two timing optimization methods: The InTime Default recipe provided by the InTime FPGA design optimization tool and another one commonly known as a “Seed Sweep”. InTime Default is a machine learning approach that finds good synthesis and place-and-route setting combinations for a design. It shares data insights across different […]

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InTime Service promises and delivers results in 3-7 days, often successfully optimizing designs with high Worst Negative Slack (WNS). To give a clearer picture, high WNS is defined as a slack value that fails timing by more than 1ns. Here we share 5 tips when dealing with such designs. Contrary to popular belief, successfully optimizing […]

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The New InTime Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers.  However, what we as users can do, is learn how to quickly abandon builds with poor […]

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The fastest a human can run 100 meters is currently 9.58 seconds; the farthest we humans can now see is about 13 billion light-years; and the reigning supercomputer can crunch data at 93 petaflops per second. But are these the best we can do? We think not – records are meant to be broken and […]

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