Blog : timing

In a previous post, we introduced a way to predict and abandon builds at the post-placement stage, skipping time- and resource-consuming routing stages that were not likely to yield good timing results. InTime users welcomed this approach, especially those who were designing with large FPGAs. We are thrilled to add this capability for our Quartus […]

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The New InTime Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers.  However, what we as users can do, is learn how to quickly abandon builds with poor […]

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While LogicLock assignments enable users to constrain their Quartus designs’ placement locations as part of floor-planning, at Plunify we’ve always been thinking about intelligently doing targeted LogicLock adjustments to improve design performance. This idea has now been implemented into a new recipe in InTime 1.6.0 called Auto Placement. The new Auto Placement recipe performs automatic placement adjustments to […]

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