Blog : InTime

Tired of seeing over-fitting or resource utilization error messages like these? These are typical over-fitting or resource utilization error messages from Quartus, Vivado and Libero. New over-fitting feature The latest over-fitting mitigation feature in InTime can help you select the right Synthesis & Fitter parameters to mitigate these issues. Mitigations for over-fitting were already present […]

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The newest addition to the InTime family is the Libero tool which supports Microchip FPGA devices. It was first included in late 2020; since then we have been honing and “sharpening the knives”, improving the QoR which includes support for the latest Libero v12.6 release. With the latest InTime release, performance improvements for Libero designs […]

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As we bid farewell to 2020, here are 5 highly-rated InTime features added during a very eventful year. Auto Pilot – Automated recipes selection Project-specific AI database Support for Microchip FPGAs and Libero Training Data Filter – precision control of Machine Learning data New Analysis Charts – SLR Crossings, Fanout & Logic Levels Charts 1. […]

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2020 began tumultuously. Most of us went through a period of isolation, and InTime 3.0 was born in this whole new landscape. With the world opening up again, albeit gradually, we are delighted to share a rundown of the latest features in InTime 3.0. Auto Pilot – Automating ML and Recipes Selection (Auto-ML) One recurring […]

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Cloud is shaping EDA like never before. Today, we are releasing the full InTime tool on the Plunify AI Lab platform. Announcing InTime on AI Lab InTime is officially included on AI Lab as one of the tools on the Plunify Cloud eco-system. This combines the cloud’s massive compute power to the ubiquitous of AI Lab platform to benefit more […]

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At the beginning of 2017, we published an article about running “seeds” in Vivado – Who Says You Can’t Use Random Seeds In Vivado?  Although Vivado does not support the “placement cost table” feature, InTime has a feature called “Placement Exploration”, which enables similar behavior without any impact on functionality. In this post, we are going […]

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In a previous post, we introduced a way to predict and abandon builds at the post-placement stage, skipping time- and resource-consuming routing stages that were not likely to yield good timing results. InTime users welcomed this approach, especially those who were designing with large FPGAs. We are thrilled to add this capability for our Quartus […]

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The New InTime Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers.  However, what we as users can do, is learn how to quickly abandon builds with poor […]

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While LogicLock assignments enable users to constrain their Quartus designs’ placement locations as part of floor-planning, at Plunify we’ve always been thinking about intelligently doing targeted LogicLock adjustments to improve design performance. This idea has now been implemented into a new recipe in InTime 1.6.0 called Auto Placement. The new Auto Placement recipe performs automatic placement adjustments to […]

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There are prudent reasons for not using too much of the FPGA’s resources, because one almost always has to insert more logic to fix a failing timing path or a functionality bug. Even back in college, the digital systems professor made it a rule that we could only use up to 70% of the logic resources for our senior […]

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