Blog : InTime

In FPGA design, the success or failure of compilation plays a crucial role in determining the efficiency and effectiveness of the overall design process. Traditionally, designers had to invest significant time and resources into running compilations, often spanning several days, only to find out that they failed due to various reasons. However, with the advent […]

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Following 2 tumultuous years, we are glad to officially announce our post-Covid release – InTime 2022. One of the top features that is included with InTime 2022 is *drum roll*- Automated Floorplanning! Floorplanning is one of those problems where the solution can be classified either as an art or science. Even if you are a […]

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Placement and routing failures during the FPGA backend flow are frequent with many FPGA designs especially when these involve multiple physical constraints. This new whitepaper introduces the Machine-Learning(ML)-based approach implemented in the InTime toolset to transform these failures to a less complex problem of timing convergence. InTime identifies the root causes of the placement or […]

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Tired of seeing over-fitting or resource utilization error messages like these? These are typical over-fitting or resource utilization error messages from Quartus, Vivado and Libero. New over-fitting feature The latest over-fitting mitigation feature in InTime can help you select the right Synthesis & Fitter parameters to mitigate these issues. Mitigations for over-fitting were already present […]

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The newest addition to the InTime family is the Libero tool which supports Microchip FPGA devices. It was first included in late 2020; since then we have been honing and “sharpening the knives”, improving the QoR which includes support for the latest Libero v12.6 release. With the latest InTime release, performance improvements for Libero designs […]

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As we bid farewell to 2020, here are 5 highly-rated InTime features added during a very eventful year. Auto Pilot – Automated recipes selection Project-specific AI database Support for Microchip FPGAs and Libero Training Data Filter – precision control of Machine Learning data New Analysis Charts – SLR Crossings, Fanout & Logic Levels Charts 1. […]

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2020 began tumultuously. Most of us went through a period of isolation, and InTime 3.0 was born in this whole new landscape. With the world opening up again, albeit gradually, we are delighted to share a rundown of the latest features in InTime 3.0. Auto Pilot – Automating ML and Recipes Selection (Auto-ML) One recurring […]

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Cloud is shaping EDA like never before. Today, we are releasing the full InTime tool on the Plunify AI Lab platform. Announcing InTime on AI Lab InTime is officially included on AI Lab as one of the tools on the Plunify Cloud eco-system. This combines the cloud’s massive compute power to the ubiquitous of AI Lab platform to benefit more […]

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At the beginning of 2017, we published an article about running “seeds” in Vivado – Who Says You Can’t Use Random Seeds In Vivado?  Although Vivado does not support the “placement cost table” feature, InTime has a feature called “Placement Exploration”, which enables similar behavior without any impact on functionality. In this post, we are going […]

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In a previous post, we introduced a way to predict and abandon builds at the post-placement stage, skipping time- and resource-consuming routing stages that were not likely to yield good timing results. InTime users welcomed this approach, especially those who were designing with large FPGAs. We are thrilled to add this capability for our Quartus […]

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