Placement and routing failures during the FPGA backend flow are frequent with many FPGA designs especially when these involve multiple physical constraints.
This new whitepaper introduces the Machine-Learning(ML)-based approach implemented in the InTime toolset to transform these failures to a less complex problem of timing convergence. InTime identifies the root causes of the placement or the routing failures, mitigating them through adjustment of the user constraints, and setting the various options making the design place-and-route-friendly.
As the experimental results illustrate, the encountered placement and routing failures are all resolved. Additionally, timing requirements are met for over 85% of the cases through this ML-based transformation. The other 15% of the designs are processed through the traditional InTime recipes to resolve timing convergence.
The paper is organized in four sections. The first section covers the inherent and artificial root causes of placement and routing failures, while the second section introduces the ML-based approach to radically tackle these failures. The third section provides actual results on real life designs. The final section summarizes the takeaways and introduces new venues where Plunify is exploring to further the improvements of the outcome in terms of QoR (quality of results), the predictability of the schedule, human and compute resources allocation.
Click here to download the new whitepaper
Register here to download an evaluation copy of InTime.
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