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We released FPGA Expansion Pack (FEP) 1.2 today, and it is all about improving the runtime and the user experience. Here is what you can expect in this release. No Regeneration of Out-Of-Context modules In previous versions, we regenerated the IP targets of all OOC modules by default to ensure that the IP was up-to-date. […]

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At the beginning of 2017, we published an article about running “seeds” in Vivado – Who Says You Can’t Use Random Seeds In Vivado?  Although Vivado does not support the “placement cost table” feature, InTime has a feature called “Placement Exploration”, which enables similar behavior without any impact on functionality. In this post, we are going […]

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As we get new requests for AI Lab and FPGA Expansion Pack in more geographical regions like China, we are receiving feedback (and complaints) about latency and responsiveness. In anticipation of an upcoming event involving AI Lab, we ran a series of simple networking tests to determine the latency, bandwidth and in general, real-life responsiveness […]

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Introduction The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools […]

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InTime Service promises and delivers results in 3-7 days, often successfully optimizing designs with high Worst Negative Slack (WNS). To give a clearer picture, high WNS is defined as a slack value that fails timing by more than 1ns. Here we share 5 tips when dealing with such designs. Contrary to popular belief, successfully optimizing […]

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The New InTime Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers.  However, what we as users can do, is learn how to quickly abandon builds with poor […]

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With the onslaught of exciting trends in Machine Learning (ML) and Artificial Intelligence (AI), Plunify has started an initiative – AI Lab, to enable users to take advantage of cloud computing for their ML needs. http://ailab.plunify.com is our new web portal where trainers, educators, students, researchers and even enthusiasts can log on to launch pre-configured […]

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AI and Machine Learning (ML) are penetrating all industries. As AI algorithms mature, the infrastructure supporting them are maturing as well. Right now, there are ASIC, CPU, GPU and FPGA solutions available as hardware platforms to accelerate these algorithms. At Plunify, we are more familiar with FPGAs but many of us are software people at […]

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So, as an Intel FPGA user, I have an Arria 10 design. Should I upgrade to Quartus 17.0? To answer this question, we used InTime tool to run through 60 different synthesis and place-and-route parameter configurations were generated by our Default recipe. Method We used an Arria 10 design (Device: 10AX115U3F45E2SGE3) for the experiment. The test was […]

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Besides fixing a few bugs, for example, in the Clock Margin recipe introduced in version 2.3,  the new features for InTime 2.4 mainly focus on providing more convenience and enhancing usability. Here is a quick summary. Auto detect FPGA tool chain and license information One of the biggest issues faced by users in large organizations […]

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