Recently we had an opportunity to optimize an FFT design generated from the Intel DSP Builder tool (in conjunction with MatLab and Simulink). This is an interesting project because the designer did not develop the RTL but generated the RTL from DSP Builder. Therefore a lot of the performance depends on how good the generated […]
Tag: Stratix10
In a previous post, we introduced a way to predict and abandon builds at the post-placement stage, skipping time- and resource-consuming routing stages that were not likely to yield good timing results. InTime users welcomed this approach, especially those who were designing with large FPGAs. We are thrilled to add this capability for our Quartus […]