General

Any serious hardware or software development effort will have a regression test suite. Continuous integration, automated daily tests, manually-executed scripts, etc. represent the different ways in which developers define, create and run validation procedures to determine the quality, performance and/or reliability of products. This article focuses on those tests that require constant (re-)compilation of FPGA […]

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As we get new requests for AI Lab and FPGA Expansion Pack in more geographical regions like China, we are receiving feedback (and complaints) about latency and responsiveness. In anticipation of an upcoming event involving AI Lab, we ran a series of simple networking tests to determine the latency, bandwidth and in general, real-life responsiveness […]

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You may think that it’s impossible to run Vivado on a lightweight machine like a Chromebook. After all, FPGA design is a compute-heavy task that is only practical with your company’s workstations and high-performance servers. So how do we do it? Mission Impossible? Okay, we confess; We can’t bend the laws of physics so we […]

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Plunify’s newest FPGA Expansion Pack for Vivado is the latest addition to a suite of cloud-enabled tools on Plunify Cloud. This tool was created for FPGA designers who have explored and are ready or perhaps have already adopted the cloud. They can relate easily to the following account of a typical customer’s experience. Plunify has been […]

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Today we announce an exciting new partnership with Xilinx to provide on-demand licenses of the best-in-class Vivado Design Suite HLx Editions software on the Plunify Cloud. Plunify Cloud is built upon the largest cloud provider – Amazon Web Services. What you can look forward to under the new Plunify-Xilinx agreement is a cloud-based platform encompassing […]

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Introduction The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools […]

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AI and Machine Learning (ML) are penetrating all industries. As AI algorithms mature, the infrastructure supporting them are maturing as well. Right now, there are ASIC, CPU, GPU and FPGA solutions available as hardware platforms to accelerate these algorithms. At Plunify, we are more familiar with FPGAs but many of us are software people at […]

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Plunify Cloud integrated with Xilinx® Vivado® lets you compile, optimize and test FPGA designs in the cloud directly from Vivado. With just a few button clicks, significantly accelerate your FPGA builds and achieve maximum performance with the flexibility of the cloud today — no more IT woes. Register a Plunify Cloud account and purchase credits […]

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Intel FPGA Technology Day 2017(China) has come to an end, but our journey on helping customers to optimize their design continues! In the three sessions at Shenzhen, Beijing and Chengdu, we had in-depth discussions with many industry professionals, going over how advanced Quartus is in terms of delivering massive timing improvements, and how InTime plays […]

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Optimizing design performance with InTime and Xilinx tools Executive Summary This whitepaper describes how InTime works with Xilinx software to optimize FPGA timing performance by adjusting compilation parameters and running builds in parallel. InTime uses machine learning to determine the best combination of synthesis and place-&-route settings for an FPGA design. Combined with compute servers, […]

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