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The latest news from the Plunify team

Many of us use 3rd-party IP to accelerate our development process and time-to-market. While IP reuse is certainly helpful, we see customers who are encountering timing and performance issues because of integration challenges. This problem becomes more apparent with design involving high-speed interfaces. Why High-speed Interfaces? Many of these problems have to do with designs […]

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We launched the Plunify Cloud platform in 2018 and introduced 2 new tools for FPGA designers. Corporate users can use the FPGA Expansion Pack (FEP) plugin to easily compile their designs in the cloud from Vivado. Another tool, AI Lab, allows FPGA designers to start a virtual environment in the cloud without worrying about the […]

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We are happy to announce that servers and tools on Plunify Cloud will be charged based on per-minute with effect immediately. Customers can take comfort in the fact that they will only pay for what they use instead of being rounded off to the next hour. This makes Plunify Cloud an even more cost-effective way […]

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Happy Thanksgiving! We would like to share some changes in the Plunify Cloud price per credit and in how the credits breakdown is displayed. If you have any questions, please feel free to contact us at tellus@plunify.com. Price Per Credits Change Starting immediately, the price of 1 credit will be changed to 10 cents (USD), […]

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Generated RTL code from a C-to-RTL tool is not easy to understand. Here is how to increase design performance without changing any RTL. Story High-level design enables a design to be captured in a concise and succinct manner, resulting in fewer errors and easier debugging. However, the oft-repeated concern is performance trade-off. Achieving high performance […]

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Cloud is shaping EDA like never before. Today, we are releasing the full InTime tool on the Plunify AI Lab platform. Announcing InTime on AI Lab InTime is officially included on AI Lab as one of the tools on the Plunify Cloud eco-system. This combines the cloud’s massive compute power to the ubiquitous of AI Lab platform to benefit more […]

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We released FPGA Expansion Pack (FEP) 1.2 today, and it is all about improving the runtime and the user experience. Here is what you can expect in this release. No Regeneration of Out-Of-Context modules In previous versions, we regenerated the IP targets of all OOC modules by default to ensure that the IP was up-to-date. […]

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At the beginning of 2017, we published an article about running “seeds” in Vivado – Who Says You Can’t Use Random Seeds In Vivado?  Although Vivado does not support the “placement cost table” feature, InTime has a feature called “Placement Exploration”, which enables similar behavior without any impact on functionality. In this post, we are going […]

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Any serious hardware or software development effort will have a regression test suite. Continuous integration, automated daily tests, manually-executed scripts, etc. represent the different ways in which developers define, create and run validation procedures to determine the quality, performance and/or reliability of products. This article focuses on those tests that require constant (re-)compilation of FPGA […]

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In a previous post, we introduced a way to predict and abandon builds at the post-placement stage, skipping time- and resource-consuming routing stages that were not likely to yield good timing results. InTime users welcomed this approach, especially those who were designing with large FPGAs. We are thrilled to add this capability for our Quartus […]

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