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Introduction The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools […]

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This whitepaper compares the effectiveness of two timing optimization methods: The InTime Default recipe provided by the InTime FPGA design optimization tool and another one commonly known as a “Seed Sweep”. InTime Default is a machine learning approach that finds good synthesis and place-and-route setting combinations for a design. It shares data insights across different […]

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InTime Service promises and delivers results in 3-7 days, often successfully optimizing designs with high Worst Negative Slack (WNS). To give a clearer picture, high WNS is defined as a slack value that fails timing by more than 1ns. Here we share 5 tips when dealing with such designs. Contrary to popular belief, successfully optimizing […]

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InTime Release 2.5 Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers.  However, what we as users can do, is learn how to quickly abandon builds with poor […]

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The fastest a human can run 100 meters is currently 9.58 seconds; the farthest we humans can now see is about 13 billion light-years; and the reigning supercomputer can crunch data at 93 petaflops per second. But are these the best we can do? We think not – records are meant to be broken and […]

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With the onslaught of exciting trends in Machine Learning (ML) and Artificial Intelligence (AI), Plunify has started an initiative – AI Lab, to enable users to take advantage of cloud computing for their ML needs. http://ailab.plunify.com is our new web portal where trainers, educators, students, researchers and even enthusiasts can log on to launch pre-configured […]

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AI and Machine Learning (ML) are penetrating all industries. As AI algorithms mature, the infrastructure supporting them are maturing as well. Right now, there are ASIC, CPU, GPU and FPGA solutions available as hardware platforms to accelerate these algorithms. At Plunify, we are more familiar with FPGAs but many of us are software people at […]

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Plunify Cloud integrated with Xilinx® Vivado® lets you compile, optimize and test FPGA designs in the cloud directly from Vivado. With just a few button clicks, significantly accelerate your FPGA builds and achieve maximum performance with the flexibility of the cloud today — no more IT woes. Register a Plunify Cloud account and purchase credits […]

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So, as an Intel FPGA user, I have an Arria 10 design. Should I upgrade to Quartus 17.0? To answer this question, we used InTime tool to run through 60 different synthesis and place-and-route parameter configurations were generated by our Default recipe. Method We used an Arria 10 design (Device: 10AX115U3F45E2SGE3) for the experiment. The test was […]

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Intel FPGA Technology Day 2017(China) has come to an end, but our journey on helping customers to optimize their design continues! In the three sessions at Shenzhen, Beijing and Chengdu, we had in-depth discussions with many industry professionals, going over how advanced Quartus is in terms of delivering massive timing improvements, and how InTime plays […]

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