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The latest news from the Plunify team

So, I have an Arria 10 design, should I upgrade to Quartus 17.0? To answer this question, we used InTime tool to run through 60 different synthesis and place-and-route parameter configurations were generated by our Default recipe. Method We used an Arria 10 design (Device: 10AX115U3F45E2SGE3) for the experiment. The test was conducted as follows: InTime generates […]

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Intel FPGA Technology Day 2017(China) has come to an end, but our journey on helping customers to optimize their design continues! In the three sessions at Shenzhen, Beijing and Chengdu, we had in-depth discussions with many industry professionals, going over how advanced Quartus is in terms of delivering massive timing improvements, and how InTime plays […]

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Optimizing design performance with InTime and Xilinx tools Executive Summary This whitepaper describes how InTime works with Xilinx software to optimize FPGA timing performance by adjusting compilation parameters and running builds in parallel. InTime uses machine learning to determine the best combination of synthesis and place-&-route settings for an FPGA design. Combined with compute servers, […]

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Besides fixing a few bugs, for example, in the Clock Margin recipe introduced in version 2.3,  the new features for InTime 2.4 mainly focus on providing more convenience and enhancing usability. Here is a quick summary. Auto detect FPGA tool chain and license information One of the biggest issues faced by users in large organizations […]

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From September to October 2017, Intel FPGA Technology Day (IFTD) will be held in 10 APAC cities this year, focusing on the theme of Accelerating a Smart and Interconnected World. Plunify will demonstrate how InTime can be used to increase Stratix 10 timing performance by more than 20% at Shenzhen (September 14), Beijing (September 19) […]

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The difference between passing and failing timing can be tiny, but failing by 500ps is just as frustrating as falling short by 5ns. Clock Margin Exploration is a new recipe in InTime version 2.3.0 that over-constrains the user’s design, potentially yielding better timing results without modifying the design. The idea is to apply “Clock Margin” adjustments […]

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Design Automation Conference 2017 in Austin, TX came and went before one could say, “Congress Bridge Bats!” A big Thank You to everyone who came by. It was very good getting to know you and hear about your design challenges and requirements — FPGA as well as ASIC ones. Devices and designs are both getting […]

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One popular example of a custom Tcl script in InTime is one that automatically executes multiple InTime Recipes in a user-defined order. For example, you can create a Tcl script to run InTime Recipe in the order of Hot Start -> InTime Default -> Deep Dive -> Seed Effort Level Exploration When each recipe completes, […]

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In this blog post we evaluate the performance of Vivado 2016.4 and Vivado 2017.1 using InTime. Overall, we conducted three experiments pitting 2016.4 against 2017.1. Under our test conditions, Vivado 2017.1 achieves better results, albeit the difference was slight for Experiment 1. Total Negative Slack and Worst Slack in Vivado 2017.1 were much better in Experiments […]

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Ever wondered how efficient InTime when it is helping you and your team optimize FPGA designs? When using the InTime Private Cloud, are you curious about whether your team has sufficient licenses to meet performance targets on time? Is there a need to increase the number of licenses? These questions represent important metrics for decision maker(s) […]

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