I recently had the pleasure of hearing Aaron Patzer of Mint.com speak at a Founder’s Institute event. It was about how Mint was found and their early challenges.One of the challenges he faced was similar to what we face at Plunify – security and trust Mint.com helps you manage personal finances. Their interactive, user-friendly software […]
(Reproduced from eefocus.com)Some tips on FPGA design found online, apparently contributed by an experienced designer.Thought it made some good points with respect to general ways to approach the process.很多人在学习FPGA设计，这里转载一个老鸟的博文，谈谈FPGA设计的17个小贴士。 1、状态机的问题，尽量不要写出太大的状态机，宁愿用一些小型的状态机来相互关联。 2、推荐大家使用timequest来做时序约束，好处是，它可能对你的时序约束和你的设计对照做分析，在做时序分析之前，先对你的约束做分析，然后告诉你，你有多少该做的事情而没有做的（为被约束的路径）还有多少你要求做的，而没有被做的（被忽略的时序要求）。 3、对时钟的约束，要重点关注两个现象。首先是尽量少的在时钟路径上引入逻辑，否则可能造成了时钟和时钟之间的skew。另外就是一种上下沿都需要用来采集数据的时钟。对于时钟的约束有很多的地方需要注意，否则你的电路都不知道会飞到哪里去。 4、约束中最重要的一个关键，不要过约束。过约束的坏处一大堆，增加编译时间，资源使用过度，导致其他的时序问题。如果你对自己的约束有些不太放心，又或者说可能器件和器件之间会有很细微的差别，你可以给约束做一些余量，但是过约束是万万要不得的。 5、 IP的作用就是为了完成一个特定的功能，所以我们并不需要知道它是如何实现的。作为一个IP，最重要的，其实是接口，因为你最重要的是需要知道是怎么让它 工作起来，而不是它怎么工作的。所以在看文档的时候，最主要看的就是接口信号，对所有的信号的作用有一个了解。例如，NiosII CPU作为一个比较大型的模块，使用的是Avalon MM 点对点接口，它与普通的PCI接口不同的地方是，他可以支持同时多线控制。因为它没有总线的概念，不会在总线被占据的时候，其他任何通讯都无法进行。 NiosII是在SOPC builder 中被直接使用的，我们不需要知道具体有哪些信号，因为没有非常需要，我们是看不到这些接口的。在NiosII中，我们有两个Master Avalon MM 接口，一个是Instruction Master Port, 这是CPU用来读取指令的接口。CPU通过这个端口从Memory上读取指令。另一个是Data master port, 很简单，这是用来连接数据通道的。比如说你要读取的数据，你要存储的数据，都是走这个通道。这两个端口可以连接同一个内存，在这种时候需要特别小心，很有 可能自己把自己的指令给改掉了。但是反过来思考一下，其实我们可以做什么？可以按照状况改变软件代码。NiosII中还有第三个端口，这是用来做 Debug用的端口。还有其他的一些接口，比如TCM接口。我们需要知道这些接口的存在，但是不需要知道细节，只有在用到的时候再去看相关的文档就好了。 6、作为系统设计，是需要有一种粗旷型的大气魄，不需要在细节上浪费时间。你会发现很多的细节是没有意义的。并不是说我们不需要去研究细节，细节是很重要的，但是细节需要在被用到的时候才去关注就好了。 7、在使用IP的时候，会遭遇到意想不到的痛苦的。所以，尽量不要依靠假设来臆想了模块的设置。而是尽量的适应环境，来配置自己的设计。作为一个FPGA的玩家，这种依照环境来改变的能力是必须的。 […]
A few months back I began noticing ads in my email window about a tool for VHDL design called, “Sigasi HDT”. Being a hardware developer, I was naturally intrigued and looked at their website. The picture on the landing page soon had me chuckling, and as I read about Sigasi HDT and the philosophy behind […]
One of the benefits touted by Cloud Computing advocates is that besides monetary gains through economies of scale, there are also benefits for the environment. Came across an article by Reuven Cohen, a cloud computing evangelist, that tries to quantify just how green the cloud is. Data seems hard to obtain at this moment, it […]
We were asked recently by investors, users and fellow community members questions that prompted some reflecting upon where Plunify is now, and where we are heading. Perhaps surprisingly, Kirvy and I haven’t deviated much from those drawn-on-a-napkin plans that we concocted way back then. The napkins have long since disintegrated but the dream remains. Plunify […]
A Brief Plunify Simulation Tutorial The following step-by-step guide to simulation is aimed at users new to Plunify or to FPGA design in general. After a design is described in Verilog / VHDL, usually the next step is to run a simulation in order to verify if the general functionality is correct. There are many […]
Came across an interesting discussion on a LinkedIn group regarding first, DSPs in FPGAs, followed by observations on trends for future FPGAs.Highlights: How to accelerate DSP applications in FPGAs so that ASIC implementations will fall behind Custom blocks in FPGAs and how they are positioned to capture more designs Motivations of FPGA makers for putting […]
We feel like surfers in an hitherto undiscovered surfing paradise, believing that the big waves(FPGA Design in the Cloud) will come and working hard in preparation (developing Plunify’s platform) for them. When the waves come, we just have to time it right, paddle like crazy and stay in the sweet spot.But we have to create […]
Recently, one of us posted a question on a discussion forum about how important synthesis, place-and-route time to developers? There were quite a few responses; most people agreed that as FPGAs and FPGA designs get more and more complex, implementation time becomes a larger portion of the development budget or project timeline. As silicon process […]
There are certainly many ways to start an FPGA design; for example one can: Open up an editor and start coding Look for, duplicate and modify an existing reference design Which approach one chooses is probably a question of deadlines and personal preference. Our engineers, for example, learned to design by coding so if given […]