We were asked recently by investors, users and fellow community members questions that prompted some reflecting upon where Plunify is now, and where we are heading. Perhaps surprisingly, Kirvy and I haven't deviated much from those drawn-on-a-napkin plans that we concocted way back then. The napkins have long since disintegrated but the dream remains.
Plunify is a startup in the FPGA ecosystem.
Our project came about because there seemed to be too many disjointed steps for creating a working FPGA design.
The situation is still pretty true today.
IP, tools, compute resources, testing, debugging, optimization, evaluating devices, etc. make it hard for users to concentrate only on their designs. A couple of specific problems include:
- too much time is spent on synthesis, place-and-route iterations
- it is a hassle to install, maintain software and PC/server hardware
- it is not easy to compare devices across FPGA vendors
Not only are gaps present in technical areas such as benchmarking, business information like device prices and availability are often hard to come by.
Plunify is an attempt to link these pieces up and to make programmable logic design as simple as possible. In a way, our vision is to become the "Salesforce for FPGA design".
We are making an all-in-one platform to solve these problems, but as you know, small startups have to prioritize ; )
For a start, the focus is on using Cloud Computing to enable basic, online FPGA design capabilities.
Besides providing a platform that abstracts unnecessary details away from users, the cloud infrastructure also helps to speed up synthesis, place-and-route to often significant extents.
In addition, the cloud enables us to adopt a vendor-agnostic interface so that users, especially new-comers to FPGA design, won't have such steep learning curves.
Currently Plunify's beta platform supports Altera and Xilinx. Two Open Source simulators, Icarus Verilog and GHDL, are also available for simulation.
Through a web interface, anyone can implement FPGA designs in the form of Verilog, VHDL, netlists and constraints files.
Subsequently, users can compare results across different devices like this example which was done for an Open Source processor core.
Through carefully allocating Cloud Computing resources, we found that up to 75% of implementation time can be saved in some cases!
User feedback has been quite rewarding so far.
Just today, a group of students who weren't familiar about FPGA design apart from simulation, and who have no FPGA tools installed on their PCs managed to use http://www.plunify.com to create a working FPGA design within an hour!
What's really cool was that they managed to do this far from their engineering lab, and relied only on a USB modem throughout!
Going forward, we are working hard to add features based on user feedback, and hope to get more traction. In particular, we'd like to automate things like constraints testing, which are currently both tedious and perhaps not so straightforward to figure out.
Ultimately, we hope to contribute towards a more open FPGA community and simplify the use of FPGAs all over the world!