A few months back I began noticing ads in my email window about a tool for VHDL design called, “Sigasi HDT”. Being a hardware developer, I was naturally intrigued and looked at their website. The picture on the landing page soon had me chuckling, and as I read about Sigasi HDT and the philosophy behind […]
One of the benefits touted by Cloud Computing advocates is that besides monetary gains through economies of scale, there are also benefits for the environment. Came across an article by Reuven Cohen, a cloud computing evangelist, that tries to quantify just how green the cloud is. Data seems hard to obtain at this moment, it […]
We were asked recently by investors, users and fellow community members questions that prompted some reflecting upon where Plunify is now, and where we are heading. Perhaps surprisingly, Kirvy and I haven’t deviated much from those drawn-on-a-napkin plans that we concocted way back then. The napkins have long since disintegrated but the dream remains. Plunify […]
A Brief Plunify Simulation Tutorial The following step-by-step guide to simulation is aimed at users new to Plunify or to FPGA design in general. After a design is described in Verilog / VHDL, usually the next step is to run a simulation in order to verify if the general functionality is correct. There are many […]
Came across an interesting discussion on a LinkedIn group regarding first, DSPs in FPGAs, followed by observations on trends for future FPGAs.Highlights: How to accelerate DSP applications in FPGAs so that ASIC implementations will fall behind Custom blocks in FPGAs and how they are positioned to capture more designs Motivations of FPGA makers for putting […]
We feel like surfers in an hitherto undiscovered surfing paradise, believing that the big waves(FPGA Design in the Cloud) will come and working hard in preparation (developing Plunify’s platform) for them. When the waves come, we just have to time it right, paddle like crazy and stay in the sweet spot.But we have to create […]
Recently, one of us posted a question on a discussion forum about how important synthesis, place-and-route time to developers? There were quite a few responses; most people agreed that as FPGAs and FPGA designs get more and more complex, implementation time becomes a larger portion of the development budget or project timeline. As silicon process […]
There are certainly many ways to start an FPGA design; for example one can: Open up an editor and start coding Look for, duplicate and modify an existing reference design Which approach one chooses is probably a question of deadlines and personal preference. Our engineers, for example, learned to design by coding so if given […]
The phrase, “reconfigurable computing,” seems to bring to mind flexibility and freedom of choice.It seems natural that some of this flexibility should mean that developers will have all the information to target whichever programmable logic device that is best for their designs. In the FPGA world, since understanding the structure and format of bitstreams and […]
Comments from VCs and senior industry people whom we’ve talked to resonate constantly in our minds. Especially those which express concern over how we’re going to sell our simulation and PLD-matching services. For example, our goal of providing accurate technical information to simplify the process of FPGA/CPLD selection for any design might not sound too […]