(Reproduced from eefocus.com)
Some tips on FPGA design found online, apparently contributed by an experienced designer.
Thought it made some good points with respect to general ways to approach the process.
很多人在学习FPGA设计，这里转载一个老鸟的博文，谈谈FPGA设计的17个小贴士。
1、状态机的问题，尽量不要写出太大的状态机，宁愿用一些小型的状态机来相互关联。
2、推荐大家使用timequest来做时序约束，好处是，它可能对你的时序约束和你的设计对照做分析，在做时序分析之前，先对你的约束做分析，然后告诉你，你有多少该做的事情而没有做的（为被约束的路径）还有多少你要求做的，而没有被做的（被忽略的时序要求）。
3、对时钟的约束，要重点关注两个现象。首先是尽量少的在时钟路径上引入逻辑，否则可能造成了时钟和时钟之间的skew。另外就是一种上下沿都需要用来采集数据的时钟。对于时钟的约束有很多的地方需要注意，否则你的电路都不知道会飞到哪里去。
4、约束中最重要的一个关键，不要过约束。过约束的坏处一大堆，增加编译时间，资源使用过度，导致其他的时序问题。如果你对自己的约束有些不太放心，又或者说可能器件和器件之间会有很细微的差别，你可以给约束做一些余量，但是过约束是万万要不得的。
5、 IP的作用就是为了完成一个特定的功能，所以我们并不需要知道它是如何实现的。作为一个IP，最重要的，其实是接口，因为你最重要的是需要知道是怎么让它 工作起来，而不是它怎么工作的。所以在看文档的时候，最主要看的就是接口信号，对所有的信号的作用有一个了解。例如，NiosII CPU作为一个比较大型的模块，使用的是Avalon MM 点对点接口，它与普通的PCI接口不同的地方是，他可以支持同时多线控制。因为它没有总线的概念，不会在总线被占据的时候，其他任何通讯都无法进行。 NiosII是在SOPC builder 中被直接使用的，我们不需要知道具体有哪些信号，因为没有非常需要，我们是看不到这些接口的。在NiosII中，我们有两个Master Avalon MM 接口，一个是Instruction Master Port, 这是CPU用来读取指令的接口。CPU通过这个端口从Memory上读取指令。另一个是Data master port, 很简单，这是用来连接数据通道的。比如说你要读取的数据，你要存储的数据，都是走这个通道。这两个端口可以连接同一个内存，在这种时候需要特别小心，很有 可能自己把自己的指令给改掉了。但是反过来思考一下，其实我们可以做什么？可以按照状况改变软件代码。NiosII中还有第三个端口，这是用来做 Debug用的端口。还有其他的一些接口，比如TCM接口。我们需要知道这些接口的存在，但是不需要知道细节，只有在用到的时候再去看相关的文档就好了。
6、作为系统设计，是需要有一种粗旷型的大气魄，不需要在细节上浪费时间。你会发现很多的细节是没有意义的。并不是说我们不需要去研究细节，细节是很重要的，但是细节需要在被用到的时候才去关注就好了。
7、在使用IP的时候，会遭遇到意想不到的痛苦的。所以，尽量不要依靠假设来臆想了模块的设置。而是尽量的适应环境，来配置自己的设计。作为一个FPGA的玩家，这种依照环境来改变的能力是必须的。
8、考虑Cashes的设置，Cash 有两种，一种是用来做指令缓存的，一种是用来做数据缓存的。Cash的大小对程序的运行速度是有影响的。当然也没必要使用过多的资源。够用就好了。
9、自定义指令设置。这是最有价值的设置。所谓自定义指令，并不是一个软件宏或者函数。而是一块硬件。当CPU调用到这个指令的时候，事实上它调用的就是这个硬件模块，它被嵌入在CPU中。而这其实就是NiosII好玩的地方。
10、SOPC builder是QuartusII中用来建立，开发，维护系统的平台。虽然很多时候我们用它作为NiosII的一个嵌入式系统的开发环境，但我不要把思路只是局限在NiosII上面。它将成为一个包容全部系统内容的一个平台。
11、 Avalon接口分成两种，一种是Avalon-MM接口，另一种是Avalon-ST 接口。MM接口，是通过地址来读写数据，更多的是用在控制逻辑上面。ST接口是用于点到点的流数据接口，更多的可以用在有高速通过率的模块中间。这两个接 口本身并没有矛盾，不是说势不两立的，一个模块中既可以有MM接口，甚至几个MM接口，也可以同时存在ST接口。作为一个点对点的接口定义，Avalon 可以做到高效的接口效果。这与PCI之类的总线接口是有本质区别的。PCI总线可以看作是铁路轨道，当一个火车在轨道上行驶的时候，就不可以有另一个火车 同时使用轨道。Avalon接口更多好像高速公路，车辆可以双向行驶。
12、作为FPGA设计中比较独特的一个原则就是，这个世界不是你创造的，所以你必须去适应它，而不是顽固自己的意图。
13、在FPGA中，除了门与门之间的延迟是固定的（时钟频率）外，一切的组合电路的延迟都是不确定的。记住这样一个规律就好了，凡是没有被门关过的信号都是不稳定的，都只是暂时的。
14、在生成新的再生门（一些逻辑的结果作为时钟去驱动一个门，我们且管他叫作再生门吧）之前，你最好把这个时钟信号用原来的那种门在关一下。这样你获得的会是一个干净的，纯粹的时钟信号。
15、针对新的一些器件，器件本身可以提供一些时钟控制模块，当你需要使用门锁（gated lock）的时候，尽量的使用这些模块，会让你的时钟变得安全（clock control block）。
16、如果你不得不使用逻辑电路来锁门，而你的器件又没有特定的模块。那么最好的情况就是，你可以先用那个时钟，把你的门锁信号关一下。这样的好处就是可以把毛刺信号完全的规避在门外面，使你的时钟更加安全。
17、上电初始值
在通常的状况下，所有的门在上电的时候输出为低。但是这并不是不能改变的。你可以把上电设置为高，这样综合工具可能会做两种事情，把输出反向，或者使用preset控制（如果存在的话）把初始值放进门里。
当时上电为高的做法，并不是非常必要，因为你其实是可以使用复位信号来获得你想要的初始状态的。
Many people are learning FPGA design, and here are some tips from an old hand.
1、Try not to have large state machines, but rather smaller ones that communicate with one another.
2、 It is recommended that Timequest is used to create timing constraints. The benefit is, before it analyzes your timing, it will first analyze your constraints and then inform you about unconstrained paths and timing requirements that you haven't attended to.
3、 Two things are worth noting with regards to clock constraints. First, as much as possible avoid inserting logic into the clock path, otherwise clock-to-clock skew may occur. Second, be very careful when gathering data on both edges of a clock, otherwise your circuit might well end up in lalaland.
4、 The most critical point in constraining is not to over-constrain. There are many pitfalls of doing so--increased compile time, utilizing more chip resources than necessary, all resulting in other timing problems. If you're concerned about your constraints, or if there are minute differences in timing characteristics from device to device, try giving more allowance in your constraints, but never over-constrain.
5、 The purpose of IP is to fulfill a specific function, so we don't have to know how a particular piece of IP works. The most important aspect of an IP core is its interface because that's all you need to make it work for you. Hence the most important section of an IP core datasheet is its interface chapter.
For example, Altera's NIOS-II CPU is a somewhat large module which uses an Avalon MM point-to-point interface. It differs from a "normal" PCI interface in that it is a simultaneous multi-master interface.
The NIOS-II is directly invoked and used within the SOPC Builder software. We don't need to know what signals it contains, for we won't be able to see those internal interfaces unless there is a real need to do so. In the NIOS-II, we have two Master Avalon MM interfaces, one of which is an Instruction Master Port--used by the CPU to fetch instructions from memory.
The other is the Data Master Port; simply put, this is used to connect datapaths. For instance the data you'd like to read and the data you'd like to save both use this datapath.
These two ports can be linked to the same internal storage. However, in that situation great care must be taken to avoid overwriting your own instructions. But thinking about it, what can we do with such an implementation? We can change our software code depending on the situation.
NIOS-II has a third port that is used for Debug, plus some other interfaces like the ITCM. We need to know that those interfaces exist but we don't need to know the details until we actually use them. When that time comes, we just need to consult the datasheet.
6、 A system designer needs to be bold and daring, and not waste time on details. You will find that many details are meaningless. This is not saying that we don't have to look into the details; details are very important, but they need to be given attention only when they are utilized.
7、 The use of IP brings with it many unpredictable issues and pain. Hence, as much as possible, don't rely on assumptions to guess a module's setup. Instead, adapt to the situation in order to deploy one's own design. This kind of improvisation is essential for an FPGA user.
8、 Consider the cache configuration. There are two types of caches--instruction caches and data caches. Their size affect software execution speed. But there's also no need to use too many resources for caches. Just enough will do.
9、 Configuring custom, user-defined instructions. This is the most valuable type of setup. A user-defined instruction in this case does not refer to a software macro or function, but to a piece of hardware. When the CPU invokes this instruction, it is invoking a hardware module which in embedded in the CPU. That's the fun of NIOS-II.
10、 SOPC Builder is a platform within Quartus-II that's used to build, develop and maintain systems. Even though we often use it as a development environment for a NIOS-II embedded system, let's not limit our thoughts about it to just a NIOS-II platform, but rather as a platform for an entire system.
11、 There are two kinds of Avalon interfaces, Avalon-MM and Avalon-ST. The former is used to read/write data via addresses and is more used for controlling logic. The latter is for point-to-point streaming data, more for use inside high-speed filter modules. These two interfaces aren't contradicting or mutually exclusive, and can co-exist in the same module. There can even be multiple MM interfaces. As a point-to-point interface, the Avalon interface can achieve high throughput. It is fundamentally different from a PCI interface; think of a PCI interface as a railway track--only one train can travel on it at a time. An Avalon interface is like a highway--multiple cars can travel on it in two different directions.
12、 A rather special principle of FPGA design is that the world wasn't made by you, so you must adapt to circumstances and not stubbornly stick to your own intentions.
13、 In an FPGA, apart from gate-to-gate delays which are fixed(clock frequency), all other combinational circuit delays are uncertain. Just remember this rule: all signals that aren't gated are unstable and temporary.
14、 Before generating a gated clock(using the result of some logic as a clock to drive a gate), you'd better use the same primary clock signal as an input to the gate that generates the gated clock signal. This way, you get a clean clock signal.
15、 Newer devices have embedded clock control modules. When you need to use gated locks, try to use those modules as much as possible. That will allow your clock to become stable.
16、 If you have no choice but to use a logic circuit to lock a gate and your device doesn't have specialized modules, then the best thing to do is to use that clock to gate your gated lock signal. That way, glitches are prevented and your clock becomes more stable.
17、 Under normal conditions, the initial output values of gates at power-up are low. But those can be changed. You can configure power-up values to be high. This kind of integrated tool can do two things--either reverse the output or use some sort of preset control (if it exists) to configure the gate with the desired initial value.
This is not really necessary because you can actually use reset signals to get the initial conditions that you want. If you really have to, there are several ways to do it... (the rest is cut off)