Doubling Fmax for Automotive Radar systems – overcoming FPGA Optimization limits

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Doubling Fmax for Automotive Radar systems – overcoming FPGA Optimization limits

surpass FPGA optimization limits

The fastest a human can run 100 meters is currently 9.58 seconds; the farthest we humans can now see is about 13 billion light-years; and the reigning supercomputer can crunch data at 93 petaflops per second. But are these the best we can do? We think not – records are meant to be broken and limitations should never stop us from trying harder.

FPGA experts from a Fortune 500 electronics company in Japan recently proved this, with careful application of machine learning. While developing an automotive radar system using an Intel PSG(Altera) Cyclone V GX device, they combined InTime with excellent design methodology to optimize the design’s performance beyond what was previously possible.

Modern automotive radar systems perform searching, identification, tracking and surveillance functions – all of which require efficient signal-processing (see example below). In a typical system like this, the FPGA serves as a hardware accelerator for radar functions.

The main IP blocks involved in such a design are:

  • floating-point FFT hardware accelerator;
  • digital beamformer; and
  • fixed-point FIR filter.

The embedded NIOS II processor serves as a host, and functional verification on real hardware can be done via specialized interfaces if desired.

automotive_digital_radar_ref_design

Figure 1: Automotive reference design diagram (Source)

Naturally for such systems, the higher the maximum frequency per Watt is, the better. In this project, the design team’s junior engineers first came up with a proof of concept that ran at 50MHz. Subsequently, senior engineers in the optimization team spent 2 weeks optimizing the design by improving the RTL and ended up more than doubling the frequency to 106MHz. Satisfied with their architectural enhancements, the optimization team turned to their next weapon — InTime. Experienced team members understood that clever use of synthesis and place-and-route would get even more performance out of their FPGA design.

Building upon the RTL enhancements to get from 50MHz to 106MHz, the optimization engineers then used InTime to achieve a new maximum frequency of 137MHz (29.2% increase) in just 2 more days without any RTL changes.

FPGA Optimization Comparison

Table 1: Design Optimization Approaches That Keep Surpassing the Limits

We believe that, combined with good RTL practices, meticulous use of the FPGA tools can further optimize every FPGA design out there. Start getting exceptional results today. Read more about InTime.

“Technology is nothing. What’s important is that you have a faith in people, that they’re basically good and smart, and if you give them tools, they’ll do wonderful things with them.” – Steve Jobs [1]

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