In FPGA design, the success or failure of compilation plays a crucial role in determining the efficiency and effectiveness of the overall design process. Traditionally, designers had to invest significant time and resources into running compilations, often spanning several days, only to find out that they failed due to various reasons. However, with the advent […]
Author: Kirvy Teo
Following 2 tumultuous years, we are glad to officially announce our post-Covid release – InTime 2022. One of the top features that is included with InTime 2022 is *drum roll*- Automated Floorplanning! Floorplanning is one of those problems where the solution can be classified either as an art or science. Even if you are a […]
Placement and routing failures during the FPGA backend flow are frequent with many FPGA designs especially when these involve multiple physical constraints. This new whitepaper introduces the Machine-Learning(ML)-based approach implemented in the InTime toolset to transform these failures to a less complex problem of timing convergence. InTime identifies the root causes of the placement or […]
Tired of seeing over-fitting or resource utilization error messages like these? These are typical over-fitting or resource utilization error messages from Quartus, Vivado and Libero. New over-fitting feature The latest over-fitting mitigation feature in InTime can help you select the right Synthesis & Fitter parameters to mitigate these issues. Mitigations for over-fitting were already present […]
The newest addition to the InTime family is the Libero tool which supports Microchip FPGA devices. It was first included in late 2020; since then we have been honing and “sharpening the knives”, improving the QoR which includes support for the latest Libero v12.6 release. With the latest InTime release, performance improvements for Libero designs […]
As we bid farewell to 2020, here are 5 highly-rated InTime features added during a very eventful year. Auto Pilot – Automated recipes selection Project-specific AI database Support for Microchip FPGAs and Libero Training Data Filter – precision control of Machine Learning data New Analysis Charts – SLR Crossings, Fanout & Logic Levels Charts 1. […]
2020 began tumultuously. Most of us went through a period of isolation, and InTime 3.0 was born in this whole new landscape. With the world opening up again, albeit gradually, we are delighted to share a rundown of the latest features in InTime 3.0. Auto Pilot – Automating ML and Recipes Selection (Auto-ML) One recurring […]
Ever wondered how InTime works? We are happy to announce that InTime is now available for download, with immediate effect. Anyone with a Plunify account can log on and download InTime from https://cloud.plunify.com. Even if you don’t have an account, you can sign up for one immediately. (and get 25 free cloud credits) After downloading […]
Recently we had an opportunity to optimize an FFT design generated from the Intel DSP Builder tool (in conjunction with MatLab and Simulink). This is an interesting project because the designer did not develop the RTL but generated the RTL from DSP Builder. Therefore a lot of the performance depends on how good the generated […]
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Prelude to 2019 – Xilinx FPGA Toolchain Comparison: Vivado 2017.4 versus 2018.3
While we wait for the release of 2019 version of Vivado, we realize that we have missed our annual Vivado comparison post. So here is the Vivado 2017.4 versus 2018.3 edition. For previous year’s results, please click here. The methods are the same as before. We use a modified version of the Vivado example “CPU” […]