InTime

Ever wondered how efficient InTime when it is helping you and your team optimize FPGA designs? When using the InTime Private Cloud, are you curious about whether your team has sufficient licenses to meet performance targets on time? Is there a need to increase the number of licenses? These questions represent important metrics for decision maker(s) […]

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Introduction One of our most common customer requests is for a smaller number of compilation runs to get to timing closure. For example, can InTime meet timing in 50 runs instead of 100 on average? Well, that depends; InTime generally has an idea of what settings will help your design meet timing, and in rare cases […]

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If you are reading this, the odds are that you or someone in your company is facing / has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application. Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified […]

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We are excited to announce the release of a new feature – Central Database (CD), in InTime. In previous versions of InTime, the visibility of compilation and analysis results is limited to individual users.  With CD, it gathers design data more efficiently across multiple users and different projects within your organization and enables sharing across different workstations and users. Below is […]

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Hi! We are happy to announce that InTime now supports the inheritance of Auto Placement assignments. This means that LogicLock or LogicLock Plus assignments created via the Auto Placement recipe will be passed onto its child revisions. For example, Tommy ran his design in InTime for three rounds. 1st round  : InTime Default 2nd round: Auto Placement 3rd […]

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Based on feedback, we understand that it is sometimes not easy for users to send us InTime log files when they encounter an issue. This is because the log files may contain what is seen as confidential information. In order to set our customers at ease, we have included a Tcl script to replace sensitive […]

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The Auto Placement recipe in InTime now supports Quartus Prime Pro Edition (in addition to Quartus-II and Quartus Prime Std Edition). Recall from Automatic placement adjustments in Quartus that the Auto Placement recipe analyses the locations of failing timing paths, and re-locates them based on what the tool learns about the design’s characteristics, without changing any source […]

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While LogicLock assignments enable users to constrain their Quartus designs’ placement locations as part of floor-planning, at Plunify we’ve always been thinking about intelligently doing targeted LogicLock adjustments to improve design performance. This idea has now been implemented into a new recipe in InTime 1.6.0 called Auto Placement. The new Auto Placement recipe performs automatic placement adjustments to […]

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There are prudent reasons for not using too much of the FPGA’s resources, because one almost always has to insert more logic to fix a failing timing path or a functionality bug. Even back in college, the digital systems professor made it a rule that we could only use up to 70% of the logic resources for our senior […]

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It is common knowledge that Vivado uses an analytical place and route engine for better and more predictable design closure, and in the process, got rid of the “cost table” (also commonly known as random seeds) user options. What may be less well-known is that designers still have ways to introduce randomness into Vivado placement, and […]

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