InTime

While LogicLock assignments enable users to constrain their Quartus designs’ placement locations as part of floor-planning, at Plunify we’ve always been thinking about intelligently doing targeted LogicLock adjustments to improve design performance. This idea has now been implemented into a new recipe in InTime 1.6.0 called Auto Placement. The new Auto Placement recipe performs automatic placement adjustments to […]

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There are prudent reasons for not using too much of the FPGA’s resources, because one almost always has to insert more logic to fix a failing timing path or a functionality bug. Even back in college, the digital systems professor made it a rule that we could only use up to 70% of the logic resources for our senior […]

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It is common knowledge that Vivado uses an analytical place and route engine for better and more predictable design closure, and in the process, got rid of the “cost table” (also commonly known as random seeds) user options. What may be less well-known is that designers still have ways to introduce randomness into Vivado placement, and […]

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InTime version 1.5.11 is officially launched today. We haven’t been describing our last few releases as we have been fine-tuning them based on customers’ requirements. Today, we are proud to finally announce these improvements! “Deep Dive” recipe This recipe was born out of the differences in the results between InTime’s “Default” recipe and its “Placement Seed […]

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Oh! The paint hasn’t dried on my Vivado 2016.1 blogpost and 2016.2 is already out! The early months of 2016 saw the release of Vivado 2016.1. We naturally assumed that it would be better than the previous version, given what we heard from beta users and developers. In many cases, users usually base their opinions […]

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Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (“Quartus”) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project. Will Quartus always run Partition Merge? If not, why?Quartus tries […]

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An evaluation customer made an interesting comment recently. Due to the rigorous nature of InTime’s approach, we’d often get comments like, “You mean this takes 100 compilations more than usual?!” This time it was, “I need to evaluate InTime more as it met timing too quickly.” It felt like a compliment hidden within a complaint, […]

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One of the questions that FPGA designers wonder and sometimes even argue about, is: Should the implementation tools focus on Worst Slack (WS) or Total Negative Slack (TNS)? FPGA tools typically devote more attention to WS, but there are tradeoffs. If WS is small yet many paths fail timing, then TNS can be huge. Similarly, […]

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Last month we released InTime v1.2, and we’ve been pushing out a number of incremental updates ever since. While the past few versions have been all about introducing new kick-ass features into InTime, this time we focused on working out the kinks. Here are the highlights of this version. New “Seeded Effort Level Exploration” Recipe Like […]

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Solving timing problems via software tools has always been the exclusive domain of the FPGA vendors. As designers, we are conditioned to run timing analysis, examine timing reports and then close timing by changing RTL and constraints. Occasionally, (favorite tip received so far), I’m told to update the FPGA software to the newest version or […]

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