Another round of holidays is upon us--today being the 2nd day of the Chinese New Year, a super long weekend in Singapore.
With little distinction of working days versus rest-days, we plod along as usual.
On the simulation side of things, we have been extremely blessed with expert beta-testers--friends and former colleagues who have devoted their free time to breaking our simulation platform. In the beginning, it was like slicing a hot knife through butter. (Despite our best efforts, nothing beats having a user to test one's code) After a couple of "Oh..." moments, the system is taking shape nicely.
Now we say with greater confidence that you should be able to log in, upload your HDL code, and run a simulation successfully. At no charge, of course.
Next, our online "Match-your-design-with-a-PLD" attempt; As of now, we have several hundred FPGAs and CPLDs in our servers, crunching happily on small designs that we downloaded off the web. Some tests error out quickly because of parameters that we neglected, whereas some run to completion successfully. It is too premature to be of interest--not even alpha, but things look encouraging.