One of the questions that FPGA designers wonder and sometimes even argue about, is: Should the implementation tools focus on Worst Slack (WS) or Total Negative Slack (TNS)?
FPGA tools typically devote more attention to WS, but there are tradeoffs. If WS is small yet many paths fail timing, then TNS can be huge. Similarly, if TNS is slight but WS is failing by a lot, that is also a problem.
To answer this question, we added a feature to collate the data for both timing values and ran about 1000 compilations on a small design (Cyclone V, about 9% utilization) using different synthesis and fitter settings.
This is what we see. The default result is marked by the black dot. The Y-axis represents the absolute value of the TNS and the X-axis, the absolute value of failing WS.
The chart is divided into 4 quadrants, green means these compilations give better TNS and WS compared to the original design.
Besides looking like a pretty smattering of colored dots, we can see that the TNS flattens out when it is closer to zero but the worst slack still keeps improving.
Taking a closer look,
What do you think?
Make your own conclusions, and please share your thoughts with us!