Plunify 2016 – H1 Newsletter

General

Plunify 2016 – H1 Newsletter

In this edition we have some exciting updates about our new office in East Singapore, new Sales Reps onboard, an exciting investment announcement and last but not least, the upcoming release of InTime version 1.4.4.

Plunify opens new headquarters in eastern Singapore
Plunify appoints new reps in Beijing and Israel
New InTime software version 1.4.4 released
InTime now supports latest Vivado version 2016.1
Plunify closese funding to enhance FPGA design timing closure capabilities
Free InTime evaluation and hands-on training

Plunify opens new headquarters in eastern Singapore

From our western origin, we crossed the island and set up base in the Aljunied area of Singapore. Now we are in a brand new building, "Atrix", with a cosy loft and a facility to beat the heat in the form of a swimming pool. We are also making arrangements for a training facility where you can come and experience the inTime software and get your hands dirty working on various timing closure problems.

Part of our expansion plans includes opening new RnD offices in Kuala Lumpur, Chengdu and Nanjing. We are hiring engineers and sales staff in all these areas.

If you are in Singapore and fancy a dip in our new, cool swimming pool, let us know! Only if you promise to bring the drinks!





Plunify appoints new sales representatives in Beijing and Israel

We would like to welcome new sales representative, the Satris Group, in Israel. Satris is a leading distributor of EDA products in Israel, providing sales, marketing and technical support services for the products it represents. It was set up by a group of EDA veterans with deep knowledge of the Israeli market, its customers and its needs. Satris’ team is well known for its high level of technical expertise and also offers advanced design and verification services, providing Israeli customers with a full, high quality solution. 

Not far from home, we would also like to welcome onboard our new partner in Beijing China, Beijing Hontak Technology. They were excited to take Plunify to their customers given the unique value proposition which only Plunify can offer to FPGA designers.

New InTime software version 1.4.4 released

In the latest version of the InTime software version 1.4.4, we have added further optimizations in the "Extra Opt Exploration" recipe. If you hit a roadblock running the default InTime recipe to get better timing results, try this new recipe that uses additional non-project flows recommended by Vivado. Some of these additional timing closure optimizations include:

  • High-fanout Optimization (Default)
  • Placement-Based Optimization (Default)
  • Rewire
  • Critical-cell Optimization
  • DSP Register Optimization
Xilinx user guide 904 gives a good idea about the available options for running the iterative flows. InTime uses these flows as part of its machine learning algorithm to achieve timing closure, allowing users to take advantage of non-standard Vivado flows alongside the machine learning capabilities of InTime. "We believe this option will result in significant improvement in the timing performance with very complex designs meeting the timing requirements," says Harnhua Ng, VP of Engineering.

InTime supports latest Vivado version 2016.1

InTime now supports the latest update from Xilinx Vivado software version 2016.1. We added the support for the new Ultrascale devices for both Kintex and Zynq devices. As 2016.1 is relatively new, we are working on comparing this version with the older 2015.4. Watch out for our report!

Plunify Closes Funding Round to Enhance FPGA Design Timing Closure Capabilities

The investment will be used to scale Plunify’s sales and technical support channels, as well as extend its marketing reach to promote its InTime software and educate FPGA design companies on how to use InTime to solve design problems and speed up their products’ Time to Market.

Read the complete funding announcement here.

Free evaluation and hands on training

To get your hands on the InTime software and free hands-on training, just drop us an email at tellus@plunify.com. We will get in touch with you shortly after. You can also visit our office to try out some of the existing designs to see how Plunify helps to close timing issues in different designs on both Altera and Xilinx FPGAs.

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