If you are reading this, the odds are that you or someone in your company is facing/has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application.
Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified people to speak about this topic. Click here to view his perspectives on.
Topics covered in this whitepaper
- Planning for timing closure.
- The vendor tools do a remarkably good job at design compilation for the general case but sometimes they can fall short.
- Why is timing closure so difficult for the vendor FPGA compilation tools?
- What to do if you cannot achieve timing closure?
- How does the InTime timing closure tool help?