While we wait for the release of 2019 version of Vivado, we realize that we have missed our annual Vivado comparison post. So here is the Vivado 2017.4 versus 2018.3 edition. For previous year’s results, please click here. The methods are the same as before. We use a modified version of the Vivado example “CPU” […]
Author: Kirvy Teo
Many of us use 3rd-party IP to accelerate our development process and time-to-market. While IP reuse is certainly helpful, we see customers who are encountering timing and performance issues because of integration challenges. This problem becomes more apparent with design involving high-speed interfaces. Why High-speed Interfaces? Many of these problems have to do with designs […]
We are happy to announce that servers and tools on Plunify Cloud will be charged based on per-minute with effect immediately. Customers can take comfort in the fact that they will only pay for what they use instead of being rounded off to the next hour. This makes Plunify Cloud an even more cost-effective way […]
Leave a comment Cloud, FPGA Expansion Pack, Plunify Cloud
Plunify Cloud: Updates to Server Types, Pricing and Credits
Happy Thanksgiving! We would like to share some changes in the Plunify Cloud price per credit and in how the credits breakdown is displayed. If you have any questions, please feel free to contact us at tellus@plunify.com. Price Per Credits Change Starting immediately, the price of 1 credit will be changed to 10 cents (USD), […]
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FPGA Expansion Pack 1.2 – All about runtime!
We released FPGA Expansion Pack (FEP) 1.2 today, and it is all about improving the runtime and the user experience. Here is what you can expect in this release. No Regeneration of Out-Of-Context modules In previous versions, we regenerated the IP targets of all OOC modules by default to ensure that the IP was up-to-date. […]
At the beginning of 2017, we published an article about running “seeds” in Vivado – Who Says You Can’t Use Random Seeds In Vivado? Although Vivado does not support the “placement cost table” feature, InTime has a feature called “Placement Exploration”, which enables similar behavior without any impact on functionality. In this post, we are going […]
As we get new requests for AI Lab and FPGA Expansion Pack in more geographical regions like China, we are receiving feedback (and complaints) about latency and responsiveness. In anticipation of an upcoming event involving AI Lab, we ran a series of simple networking tests to determine the latency, bandwidth and in general, real-life responsiveness […]
Introduction The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools […]
InTime Service promises and delivers results in 3-7 days, often successfully optimizing designs with high Worst Negative Slack (WNS). To give a clearer picture, high WNS is defined as a slack value that fails timing by more than 1ns. Here we share 5 tips when dealing with such designs. Contrary to popular belief, successfully optimizing […]
The New InTime Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers. However, what we as users can do, is learn how to quickly abandon builds with poor […]