tldr version:- Vivado’s default floorplan had bad timing.- Customer ran implementation directives and created their own floorplans, but was still unable to meet the timing target.- We improved customer’s floorplan by generating new intra-die (SLR) floorplans.- Finally met the timing target using our floorplan and implementation directives. Why Floorplan? Vivado’s decision to place certain instance […]
Tag: Vivado
Following 2 tumultuous years, we are glad to officially announce our post-Covid release – InTime 2022. One of the top features that is included with InTime 2022 is *drum roll*- Automated Floorplanning! Floorplanning is one of those problems where the solution can be classified either as an art or science. Even if you are a […]
Placement and routing failures during the FPGA backend flow are frequent with many FPGA designs especially when these involve multiple physical constraints. This new whitepaper introduces the Machine-Learning(ML)-based approach implemented in the InTime toolset to transform these failures to a less complex problem of timing convergence. InTime identifies the root causes of the placement or […]
Tired of seeing over-fitting or resource utilization error messages like these? These are typical over-fitting or resource utilization error messages from Quartus, Vivado and Libero. New over-fitting feature The latest over-fitting mitigation feature in InTime can help you select the right Synthesis & Fitter parameters to mitigate these issues. Mitigations for over-fitting were already present […]
As we bid farewell to 2020, here are 5 highly-rated InTime features added during a very eventful year. Auto Pilot – Automated recipes selection Project-specific AI database Support for Microchip FPGAs and Libero Training Data Filter – precision control of Machine Learning data New Analysis Charts – SLR Crossings, Fanout & Logic Levels Charts 1. […]
2020 began tumultuously. Most of us went through a period of isolation, and InTime 3.0 was born in this whole new landscape. With the world opening up again, albeit gradually, we are delighted to share a rundown of the latest features in InTime 3.0. Auto Pilot – Automating ML and Recipes Selection (Auto-ML) One recurring […]
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Prelude to 2019 – Xilinx FPGA Toolchain Comparison: Vivado 2017.4 versus 2018.3
While we wait for the release of 2019 version of Vivado, we realize that we have missed our annual Vivado comparison post. So here is the Vivado 2017.4 versus 2018.3 edition. For previous year’s results, please click here. The methods are the same as before. We use a modified version of the Vivado example “CPU” […]
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Announcing Micropayments – High Performance Cloud Experience Starting from $2.89
We launched the Plunify Cloud platform in 2018 and introduced 2 new tools for FPGA designers. Corporate users can use the FPGA Expansion Pack (FEP) plugin to easily compile their designs in the cloud from Vivado. Another tool, AI Lab, allows FPGA designers to start a virtual environment in the cloud without worrying about the […]
Generated RTL code from a C-to-RTL tool is not easy to understand. Here is how to increase design performance without changing any RTL. Story High-level design enables a design to be captured in a concise and succinct manner, resulting in fewer errors and easier debugging. However, the oft-repeated concern is performance trade-off. Achieving high performance […]
Cloud is shaping EDA like never before. Today, we are releasing the full InTime tool on the Plunify AI Lab platform. Announcing InTime on AI Lab InTime is officially included on AI Lab as one of the tools on the Plunify Cloud eco-system. This combines the cloud’s massive compute power to the ubiquitous of AI Lab platform to benefit more […]