AI and Machine Learning (ML) are penetrating all industries. As AI algorithms mature, the infrastructure supporting them are maturing as well. Right now, there are ASIC, CPU, GPU and FPGA solutions available as hardware platforms to accelerate these algorithms. At Plunify, we are more familiar with FPGAs but many of us are software people at […]
Author: Kirvy Teo
So, as an Intel FPGA user, I have an Arria 10 design. Should I upgrade to Quartus 17.0? To answer this question, we used InTime tool to run through 60 different synthesis and place-and-route parameter configurations were generated by our Default recipe. Method We used an Arria 10 design (Device: 10AX115U3F45E2SGE3) for the experiment. The test was […]
Besides fixing a few bugs, for example, in the Clock Margin recipe introduced in version 2.3, the new features for InTime 2.4 mainly focus on providing more convenience and enhancing usability. Here is a quick summary. Auto detect FPGA tool chain and license information One of the biggest issues faced by users in large organizations […]
For those who know our history, Plunify was born in the cloud. Our very first prototype of InTime was developed, executed and tested on Amazon Web Services. During those days, we only had to contend with EC2, EBS and S3. We even had to implement AES encryption in S3 ourselves (nowadays it is a checkbox!). […]
InTime version 1.5.11 is officially launched today. We haven’t been describing our last few releases as we have been fine-tuning them based on customers’ requirements. Today, we are proud to finally announce these improvements! “Deep Dive” recipe This recipe was born out of the differences in the results between InTime’s “Default” recipe and its “Placement Seed […]
Oh! The paint hasn’t dried on my Vivado 2016.1 blogpost and 2016.2 is already out! The early months of 2016 saw the release of Vivado 2016.1. We naturally assumed that it would be better than the previous version, given what we heard from beta users and developers. In many cases, users usually base their opinions […]
Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (“Quartus”) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project. Will Quartus always run Partition Merge? If not, why? Quartus […]
In this edition we have some exciting updates about our new office in East Singapore, new Sales Reps onboard, an exciting investment announcement and last but not least, the upcoming release of InTime version 1.4.4. Plunify opens new headquarters in eastern Singapore Plunify appoints new reps in Beijing and Israel New InTime software version 1.4.4 […]
Due to the rigorous nature of InTime’s approach, we’d often get comments like, “You mean this takes 100 compilations more than usual?!” An evaluation customer made an interesting comment recently. This time it was, “I need to evaluate InTime more as it met timing too quickly.” It felt like a compliment hidden within a complaint, […]
One of the questions that FPGA designers wonder and sometimes even argue about, is: Should the implementation tools focus on Worst Slack (WS) or Total Negative Slack (TNS)? FPGA tools typically devote more attention to WS, but there are tradeoffs. If WS is small yet many paths fail timing, then TNS can be huge. Similarly, […]