One of the questions that FPGA designers wonder and sometimes even argue about, is: Should the implementation tools focus on Worst Slack (WS) or Total Negative Slack (TNS)? FPGA tools typically devote more attention to WS, but there are tradeoffs. If WS is small yet many paths fail timing, then TNS can be huge. Similarly, […]
Author: Kirvy Teo
http://eecatalog.com/chipdesign/2015/02/04/the-coming-year-in-eda-what-will-shape-2015/ Hamhua Ng, CEO of Plunify said: “There is much truth in the saying, ‘Those who don’t learn from history are doomed to repeat it,’ especially in the data-driven world that we live in today. It seems like every retailer, social network and financial institution is analyzing and finding patterns in the data that we […]
EDA Past, Present, and Future with Lucio Lanza. Another amazing interview from one of our investors. http://www.eejournal.com/archives/articles/20141219-fishfry/
Last month we released InTime v1.2, and we’ve been pushing out a number of incremental updates ever since. While the past few versions have been all about introducing new kick-ass features into InTime, this time we focused on working out the kinks. Here are the highlights of this version. New “Seeded Effort Level Exploration” Recipe […]
Solving timing problems via software tools has always been the exclusive domain of the FPGA vendors. As designers, we are conditioned to run timing analysis, examine timing reports and then close timing by changing RTL and constraints. Occasionally, (favorite tip received so far), I’m told to update the FPGA software to the newest version or […]
We leapfrogged 1.1.6 because we got a ton of requests. So here is InTime version 1.1.7. What are the top 3 features worth checking out? Here’s my list. For a detailed list of changes, please see the release notes. #1 – “The Good, The Bad and the Necessary” — More control over synthesis and […]
InTime v1.1.5 was officially released on Thursday, the 8th of May. This release focused mainly of making it easier for new users to get started, and polishing up existing features. This release also contains numerous bug fixes which were reported, most significantly issues experienced by some users where specific designs failed to run property […]
Plunify collaborated with CSIP and Huada Empyrean to provide a private cloud platform for an inter-university IC design competition in China. Implemented earlier this year, the solution consists of our EDAxtend platform, but instead of FPGA tools, this implementation includes EDA tools from Huada Empyrean. In terms of specifications, this platform is designed to handle the load of […]
As we are only starting to make more information about InTime available publicly, there hasn’t been release-oriented posts until now. Going forward we’ll aim to accompany every release with a post highlighting new features as well as adding detailed release notes to the InTime documentation. If you’re not quite sure what InTime is yet, check […]
Early this year, we released InTime under a closed-door early access program to a handful of customers. From the various feedback and feature requests, it is currently undergoing a series of rapid upgrades and improvements. We are excited by the support and insights that InTime is delivering to customers. For the rest of the […]