InTime Service promises and delivers results in 3-7 days, often successfully optimizing designs with high Worst Negative Slack (WNS). To give a clearer picture, high WNS is defined as a slack value that fails timing by more than 1ns. Here we share 5 tips when dealing with such designs. Contrary to popular belief, successfully optimizing […]
The New InTime Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers. However, what we as users can do, is learn how to quickly abandon builds with poor […]
The fastest a human can run 100 meters is currently 9.58 seconds; the farthest we humans can now see is about 13 billion light-years; and the reigning supercomputer can crunch data at 93 petaflops per second. But are these the best we can do? We think not – records are meant to be broken and […]
With the onslaught of exciting trends in Machine Learning (ML) and Artificial Intelligence (AI), Plunify has started an initiative – AI Lab, to enable users to take advantage of cloud computing for their ML needs. http://ailab.plunify.com is our new web portal where trainers, educators, students, researchers and even enthusiasts can log on to launch pre-configured […]
AI and Machine Learning (ML) are penetrating all industries. As AI algorithms mature, the infrastructure supporting them are maturing as well. Right now, there are ASIC, CPU, GPU and FPGA solutions available as hardware platforms to accelerate these algorithms. At Plunify, we are more familiar with FPGAs but many of us are software people at […]
Plunify Cloud integrated with Xilinx® Vivado® lets you compile, optimize and test FPGA designs in the cloud directly from Vivado. With just a few button clicks, significantly accelerate your FPGA builds and achieve maximum performance with the flexibility of the cloud today — no more IT woes. Register a Plunify Cloud account and purchase credits […]
So, as an Intel FPGA user, I have an Arria 10 design. Should I upgrade to Quartus 17.0? To answer this question, we used InTime tool to run through 60 different synthesis and place-and-route parameter configurations were generated by our Default recipe. Method We used an Arria 10 design (Device: 10AX115U3F45E2SGE3) for the experiment. The test was […]
Intel FPGA Technology Day 2017(China) has come to an end, but our journey on helping customers to optimize their design continues! In the three sessions at Shenzhen, Beijing and Chengdu, we had in-depth discussions with many industry professionals, going over how advanced Quartus is in terms of delivering massive timing improvements, and how InTime plays […]
Optimizing design performance with InTime and Xilinx tools Executive Summary This whitepaper describes how InTime works with Xilinx software to optimize FPGA timing performance by adjusting compilation parameters and running builds in parallel. InTime uses machine learning to determine the best combination of synthesis and place-&-route settings for an FPGA design. Combined with compute servers, […]
Besides fixing a few bugs, for example, in the Clock Margin recipe introduced in version 2.3, the new features for InTime 2.4 mainly focus on providing more convenience and enhancing usability. Here is a quick summary. Auto detect FPGA tool chain and license information One of the biggest issues faced by users in large organizations […]