Intel FPGA Technology Day 2017(China) has come to an end, but our journey on helping customers to optimize their design continues! In the three sessions at Shenzhen, Beijing and Chengdu, we had in-depth discussions with many industry professionals, going over how advanced Quartus is in terms of delivering massive timing improvements, and how InTime plays […]
Optimizing design performance with InTime and Xilinx tools Executive Summary This whitepaper describes how InTime works with Xilinx software to optimize FPGA timing performance by adjusting compilation parameters and running builds in parallel. InTime uses machine learning to determine the best combination of synthesis and place-&-route settings for an FPGA design. Combined with compute servers, […]
Besides fixing a few bugs, for example, in the Clock Margin recipe introduced in version 2.3, the new features for InTime 2.4 mainly focus on providing more convenience and enhancing usability. Here is a quick summary. Auto detect FPGA tool chain and license information One of the biggest issues faced by users in large organizations […]
From September to October 2017, Intel FPGA Technology Day (IFTD) will be held in 10 APAC cities this year, focusing on the theme of Accelerating a Smart and Interconnected World. Plunify will demonstrate how InTime can be used to increase Stratix 10 timing performance by more than 20% at Shenzhen (September 14), Beijing (September 19) […]
Design Automation Conference 2017 in Austin, TX came and went before one could say, “Congress Bridge Bats!” A big Thank You to everyone who came by. It was very good getting to know you and hear about your design challenges and requirements — FPGA as well as ASIC ones. Devices and designs are both getting […]
One popular example of a custom Tcl script in InTime is one that automatically executes multiple InTime Recipes in a user-defined order. For example, you can create a Tcl script to run InTime Recipe in the order of Hot Start -> InTime Default -> Deep Dive -> Seed Effort Level Exploration When each recipe completes, […]
Xilinx FPGA Performance Evaluation for Vivado 2016.4 and Vivado 2017.1 using InTime. Overall, we conducted three experiments pitting Vivado 2016.4 against Vivado 2017.1. Under our test conditions, Vivado 2017.1 achieves slightly better results in Experiment 1, while total Negative Slack and Worst Slack in Vivado 2017.1 were much better in Experiments 2 and 3. Methods For […]
For those who know our history, Plunify was born in the cloud. Our very first prototype of InTime was developed, executed and tested on Amazon Web Services. During those days, we only had to contend with EC2, EBS and S3. We even had to implement AES encryption in S3 ourselves (nowadays it is a checkbox!). […]
If you are reading this, the odds are that you or someone in your company is facing/has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application. Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified people to […]
Based on feedback, we understand that it is sometimes not easy for users to send us InTime log files when they encounter an issue. This is because the log files may contain what is seen as confidential information. In order to set our customers at ease, we have included a Tcl script to replace sensitive […]