InTime Service promises and delivers results in 3-7 days, often successfully optimizing designs with high Worst Negative Slack (WNS). To give a clearer picture, high WNS is defined as a slack value that fails timing by more than 1ns. Here we share 5 tips when dealing with such designs. Contrary to popular belief, successfully optimizing […]
The New InTime Since day one, every customer has been hoping that we can magically reduce their designs’ compile times. Sadly, (and for the umpteenth time!) we can’t – that is still the domain of the FPGA tool makers. However, what we as users can do, is learn how to quickly abandon builds with poor […]
The fastest a human can run 100 meters is currently 9.58 seconds; the farthest we humans can now see is about 13 billion light-years; and the reigning supercomputer can crunch data at 93 petaflops per second. But are these the best we can do? We think not – records are meant to be broken and […]
So, as an Intel FPGA user, I have an Arria 10 design. Should I upgrade to Quartus 17.0? To answer this question, we used InTime tool to run through 60 different synthesis and place-and-route parameter configurations were generated by our Default recipe. Method We used an Arria 10 design (Device: 10AX115U3F45E2SGE3) for the experiment. The test was […]
Optimizing design performance with InTime and Xilinx tools Executive Summary This whitepaper describes how InTime works with Xilinx software to optimize FPGA timing performance by adjusting compilation parameters and running builds in parallel. InTime uses machine learning to determine the best combination of synthesis and place-&-route settings for an FPGA design. Combined with compute servers, […]
Besides fixing a few bugs, for example, in the Clock Margin recipe introduced in version 2.3, the new features for InTime 2.4 mainly focus on providing more convenience and enhancing usability. Here is a quick summary. Auto detect FPGA tool chain and license information One of the biggest issues faced by users in large organizations […]
The difference between passing and failing timing can be tiny, but failing by 500ps is just as frustrating as falling short by 5ns. Clock Margin Exploration is a new recipe in InTime version 2.3.0 that over-constrains the user’s design, potentially yielding better timing results without modifying the design. Use Clock Uncertainty The idea is to […]
Ever wondered how efficient InTime when it is helping you and your team optimize FPGA designs? When using the InTime Private Cloud, are you curious about whether your team has sufficient licenses to meet performance targets on time? Is there a need to increase the number of licenses? These questions represent important metrics for decision maker(s) […]
Introduction One of our most common customer requests is for a smaller number of compilation runs to get to timing closure. For example, can InTime meet timing in 50 runs instead of 100 on average? Well, that depends; InTime generally has an idea of what settings will help your design meet timing, and in rare cases […]
If you are reading this, the odds are that you or someone in your company is facing/has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application. Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified people to […]