We are excited to announce the release of a new feature – Central Database (CD), in InTime. In previous versions of InTime, the visibility of compilation and analysis results is limited to individual users. With CD, it gathers design data more efficiently across multiple users and different projects within your organization and enables sharing across different workstations and users. Below is […]
Hi! We are happy to announce that InTime now supports the inheritance of Auto Placement assignments. This means that LogicLock or LogicLock Plus assignments created via the Auto Placement recipe will be passed onto its child revisions. For example, Tommy ran his design in InTime for three rounds. 1st round : InTime Default 2nd round: Auto Placement 3rd […]
Based on feedback, we understand that it is sometimes not easy for users to send us InTime log files when they encounter an issue. This is because the log files may contain what is seen as confidential information. In order to set our customers at ease, we have included a Tcl script to replace sensitive […]
The Auto Placement recipe in InTime now supports Quartus Prime Pro Edition (in addition to Quartus-II and Quartus Prime Std Edition). Recall from Automatic placement adjustments in Quartus that the Auto Placement recipe analyses the locations of failing timing paths, and re-locates them based on what the tool learns about the design’s characteristics, without changing any source […]
While LogicLock assignments enable users to constrain their Quartus designs’ placement locations as part of floor-planning, at Plunify we’ve always been thinking about intelligently doing targeted LogicLock adjustments to improve design performance. This idea has now been implemented into a new recipe in InTime 1.6.0 called Auto Placement. The new Auto Placement recipe performs automatic placement adjustments to […]
There are prudent reasons for not using too much of the FPGA’s resources, because one almost always has to insert more logic to fix a failing timing path or a functionality bug. Even back in college, the digital systems professor made it a rule that we could only use up to 70% of the logic resources for our senior […]
It is common knowledge that Vivado uses an analytical place and route engine for better and more predictable design closure. As a result, Vivado got rid of the “cost table” (also commonly known as random seeds) user options. What may be less well-known is that designers still have ways to introduce randomness into Vivado placement. Like […]
InTime version 1.5.11 is officially launched today. We haven’t been describing our last few releases as we have been fine-tuning them based on customers’ requirements. Today, we are proud to finally announce these improvements! “Deep Dive” recipe This recipe was born out of the differences in the results between InTime’s “Default” recipe and its “Placement Seed […]
Oh! The paint hasn’t dried on my Vivado 2016.1 blogpost and 2016.2 is already out! The early months of 2016 saw the release of Vivado 2016.1. We naturally assumed that it would be better than the previous version, given what we heard from beta users and developers. In many cases, users usually base their opinions […]
Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II (“Quartus”) design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project. Will Quartus always run Partition Merge? If not, why? Quartus […]